Issue No.02 - February (2006 vol.55)
Paolo Bernardi , IEEE
Leticia Maria Veiras Bolzani , IEEE
Maurizio Rebaudengo , IEEE
Matteo Sonza Reorda , IEEE
Fabian Luis Vargas , IEEE
Massimo Violante , IEEE
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/TC.2006.15
Hardening SoCs against transient faults requires new techniques able to combine high fault detection capabilities with the usual requirements of SoC design flow, e.g., reduced design-time, low area overhead, and reduced (or null) accessibility to source core descriptions. This paper proposes a new hybrid approach which combines hardening software transformations with the introduction of an Infrastructure IP with reduced memory and performance overheads. The proposed approach targets faults affecting the memory elements storing both the code and the data, independently of their location (inside or outside the processor). Extensive experimental results, including comparisons with previous approaches, are reported, which allow practically evaluating the characteristics of the method in terms of fault detection capabilities and area, memory, and performance overheads.
Index Terms- SoC dependability, infrastructure IP, transient fault detection.
Paolo Bernardi, Leticia Maria Veiras Bolzani, Maurizio Rebaudengo, Matteo Sonza Reorda, Fabian Luis Vargas, Massimo Violante, "A New Hybrid Fault Detection Technique for Systems-on-a-Chip", IEEE Transactions on Computers, vol.55, no. 2, pp. 185-198, February 2006, doi:10.1109/TC.2006.15