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A New Hybrid Fault Detection Technique for Systems-on-a-Chip
February 2006 (vol. 55 no. 2)
pp. 185-198
ASCII Text
x 
 
Paolo Bernardi, Leticia Maria Veiras Bolzani, Maurizio Rebaudengo, Matteo Sonza Reorda, Fabian Luis Vargas, Massimo Violante, "A New Hybrid Fault Detection Technique for Systems-on-a-Chip," IEEE Transactions on Computers, vol. 55, no. 2, pp. 185-198, February, 2006.
 
 
BibTex
x
 
@article{ 10.1109/TC.2006.15,
author = {Paolo Bernardi and Leticia Maria Veiras Bolzani and Maurizio Rebaudengo and Matteo Sonza Reorda and Fabian Luis Vargas and Massimo Violante},
title = {A New Hybrid Fault Detection Technique for Systems-on-a-Chip},
journal ={IEEE Transactions on Computers},
volume = {55},
number = {2},
issn = {0018-9340},
year = {2006},
pages = {185-198},
doi = {http://doi.ieeecomputersociety.org/10.1109/TC.2006.15},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - JOUR
JO - IEEE Transactions on Computers
TI - A New Hybrid Fault Detection Technique for Systems-on-a-Chip
IS - 2
SN - 0018-9340
SP185
EP198
EPD - 185-198
A1 - Paolo Bernardi,
A1 - Leticia Maria Veiras Bolzani,
A1 - Maurizio Rebaudengo,
A1 - Matteo Sonza Reorda,
A1 - Fabian Luis Vargas,
A1 - Massimo Violante,
PY - 2006
KW - Index Terms- SoC dependability
KW - infrastructure IP
KW - transient fault detection.
VL - 55
JA - IEEE Transactions on Computers
ER -
 
Hardening SoCs against transient faults requires new techniques able to combine high fault detection capabilities with the usual requirements of SoC design flow, e.g., reduced design-time, low area overhead, and reduced (or null) accessibility to source core descriptions. This paper proposes a new hybrid approach which combines hardening software transformations with the introduction of an Infrastructure IP with reduced memory and performance overheads. The proposed approach targets faults affecting the memory elements storing both the code and the data, independently of their location (inside or outside the processor). Extensive experimental results, including comparisons with previous approaches, are reported, which allow practically evaluating the characteristics of the method in terms of fault detection capabilities and area, memory, and performance overheads.

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Index Terms:
Index Terms- SoC dependability, infrastructure IP, transient fault detection.
Citation:
Paolo Bernardi, Leticia Maria Veiras Bolzani, Maurizio Rebaudengo, Matteo Sonza Reorda, Fabian Luis Vargas, Massimo Violante, "A New Hybrid Fault Detection Technique for Systems-on-a-Chip," IEEE Transactions on Computers, vol. 55, no. 2, pp. 185-198, Feb. 2006, doi:10.1109/TC.2006.15
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