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Debug Support Strategy for Systems-on-Chips with Multiple Processor Cores
February 2006 (vol. 55 no. 2)
pp. 174-184
On-chip program and data tracing is now an essential part of any system level development platform for System-on-Chip (SoC). Current debug support solutions are platform specific and incompatible with processors and active peripherals from other sources, restricting effective design reuse. In order to overcome this reuse challenge, this paper defines interfaces to decouple the debug support from processor cores and other active data accessing units. The on-chip debug support infrastructure is also decoupled from each core's debug support and from the trace port or trace memory, using an additional interface. As a result, this decoupling of the debug support infrastructure provides freedom from a specific SoC platform. These interfaces are applied through a reference design modeled using VHDL that is based on a novel low overhead trace message framework. Compared with a leading implementation of a relevant standard, the reference design is 50 percent more compact while providing improvements in trace compression of 8.4 percent for program trace messages and almost 24 percent for data trace messages. This reference design is a multiple core solution that is compatible with most SoC architectures, including those based on emerging Network-on-Chip architectures.

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Index Terms:
Index Terms- System architectures, integration, and modeling; real-time and embedded systems; multiprocessor systems; debugging aids.
Citation:
Andrew B.T. Hopkins, Klaus D. McDonald-Maier, "Debug Support Strategy for Systems-on-Chips with Multiple Processor Cores," IEEE Transactions on Computers, vol. 55, no. 2, pp. 174-184, Feb. 2006, doi:10.1109/TC.2006.22
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