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Testing Embedded Sequential Cores in Parallel Using Spectrum-Based BIST
February 2006 (vol. 55 no. 2)
pp. 150-162
ASCII Text
x 
 
Xiaoding Chen, Michael S. Hsiao, "Testing Embedded Sequential Cores in Parallel Using Spectrum-Based BIST," IEEE Transactions on Computers, vol. 55, no. 2, pp. 150-162, February, 2006.
 
 
BibTex
x
 
@article{ 10.1109/TC.2006.30,
author = {Xiaoding Chen and Michael S. Hsiao},
title = {Testing Embedded Sequential Cores in Parallel Using Spectrum-Based BIST},
journal ={IEEE Transactions on Computers},
volume = {55},
number = {2},
issn = {0018-9340},
year = {2006},
pages = {150-162},
doi = {http://doi.ieeecomputersociety.org/10.1109/TC.2006.30},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - JOUR
JO - IEEE Transactions on Computers
TI - Testing Embedded Sequential Cores in Parallel Using Spectrum-Based BIST
IS - 2
SN - 0018-9340
SP150
EP162
EPD - 150-162
A1 - Xiaoding Chen,
A1 - Michael S. Hsiao,
PY - 2006
KW - Index Terms- System-on-a-chip
KW - built-in-self-test
KW - spectral analysis.
VL - 55
JA - IEEE Transactions on Computers
ER -
 
We present a new BIST (built-in-self-test) architecture for system-on-a-chip (SOC), which can test a cluster of embedded sequential cores simultaneously. The compressed spectrum for a cluster of cores under test is computed by performing spectral analysis individually on all cores. Because there is no need to combine the cores to extract the spectrum for the entire cluster, the computation complexity is greatly reduced. For each individual core, we propose an interleaved state relaxation on the compacted test sequence for its characteristic fault set, leading to a partially specified, interleaved sequence which can be merged in a much easier way. A delay network and a switching network are added selectively to allow for more aggressive merging of spectra. Experimental results show that the same level of fault coverage can be achieved for each individual core with negligible hardware overhead, while the test application time for testing the entire cluster can be reduced by up to four times and the test data storage requirement is reduced by up to 42 percent.

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Index Terms:
Index Terms- System-on-a-chip, built-in-self-test, spectral analysis.
Citation:
Xiaoding Chen, Michael S. Hsiao, "Testing Embedded Sequential Cores in Parallel Using Spectrum-Based BIST," IEEE Transactions on Computers, vol. 55, no. 2, pp. 150-162, Feb. 2006, doi:10.1109/TC.2006.30
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