This Article 
   
 Share 
   
 Bibliographic References 
   
 Add to: 
 
Digg
Furl
Spurl
Blink
Simpy
Google
Del.icio.us
Y!MyWeb
 
 Search 
   
Enhancing Performance of HW/SW Cosimulation and Coemulation by Reducing Communication Overhead
February 2006 (vol. 55 no. 2)
pp. 125-136
For system-level simulation of a complex system-on-chip design, multiple hardware simulators and emulators can be combined to work together. The simulation performance in this case is often limited by the communication overhead between simulators and emulators. To reduce the amount of communication in this heterogeneous simulation environment, we propose novel methods to find a time interval during which there are no transactions among simulators based on a dynamic prediction of transaction occurrence time for both software and hardware models. We also propose a simulator scheduling algorithm which allows the simulator to work alone without interaction with others when there is no transaction. By so doing, we reduced the amount of pure communication by a factor of 15 to 67 and, as a result, achieved a speed-up factor of 4 to 40 compared to existing lock-step simulation, as shown by experimental results with various application examples.

[1] L. Benini, D. Bertozzi, D. Bruni, N. Drago, F. Fummi, and M. Poncino, “SystemC Cosimulation and Emulation of Multiprocessor SoC Designs,” Computer, vol. 36, no. 4, pp. 53-59, Apr. 2003.
[2] P. Gerin, S. Yoo, G. Nicolescu, and A.A. Jerraya, “Scalable and Flexible Cosimulation of SoC Designs with Heterogeneous Multi-Processor Target Architectures,” Proc. Asia and South Pacific Design Automation Conf., pp. 63-68, 2001.
[3] J.-G. Lee, M.-K. Chung, K.-Y. Ahn, S.-H. Lee, and C.-M. Kyung, “A Prediction Packetizing Scheme for Reducing Channel Traffic in Transaction-Level Hardware/Software Co-Emulation,” Proc. Design Automation and Test in Europe, vol. 1, pp. 384-389, 2005.
[4] Y.-I. Kim and C.-M. Kyung, “TPartition: Testbench Partitioning for Hardware-Accelerated Functional Verification,” IEEE Design and Test of Computers, vol. 21, no. 6, pp. 484-493, Nov./Dec. 2004.
[5] R.E. Bryant, “Simulation of Packet Communication Architecture Computer Systems,” Technical Report TR-188, Massachusetts Inst. of Tech nology, 1977.
[6] K.M. Chandy and J. Misra, “Distributed Simulation: A Case Study in Design and Verification of Distributed Programs,” IEEE Trans. Software Eng., vol. 5, no. 5, pp. 440-452, Sept. 1978.
[7] D.R. Jefferson, “Virtual Time,” ACM Trans. Programming Languages and Systems, vol. 7, no 3, pp. 404-425, July 1985.
[8] R.M. Fujimoto, “Parallel Discrete Event Simulation,” Comm. ACM, vol. 33, no 10, pp. 30-53, Oct. 1990.
[9] T. Grotker, S. Liao, G. Martin, and S. Swan, System Design with SystemC. Kluwer Academic, 2002.
[10] M.-K. Chung, S. Yang, S.-H. Lee, and C.-M. Kyung, “System-Level HW/SW Co-Simulation Framework for Multiprocessor and Multithread SoC,” Proc. VLSI-TSA Design, Automation, and Test, pp. 177-179, 2005.
[11] O. Blaurock, “A SystemC-Based Modular Design and Verification Framework for C-Model Reuse in a HW/SW-Codesign Design Flow,” Proc. Distributed Computing Systems Workshops, pp. 838-843, 2004.
[12] G.D. Nagendra, V.G.P. Kumar, and B.S. Sheshadri, “Simulation Bridge: A Framework for Multi-Processor Simulation,” Proc. 10th Symp. Hardware/Software Codesign, pp. 49-54, 2002.
[13] R. Henftling, A. Zinn, M. Bauer, M. Zambaldi, and W. Ecker, “Re-Use-Centric Architecture for a Fully Accelerated Testbench Environment,” Proc. 40th Design Automation Conf., pp. 372-375, 2003.
[14] J. Jung, S. Yoo, and K. Choi, “Performance Improvement of Multi-Processor Systems Cosimulation Based on SW Analysis,” Proc. Design, Automation, and Test in Europe, pp. 749-753, 2001.
[15] E.W. Dijkstra, “A Note on Two Problems in Connexion with Graphs,” Numerische Mathematik, pp. 269-297, 1989.
[16] C.J. Hughes, V.S. Pai, P. Ranganathan, and S.V. Adve, “Rsim: Simulating Shared-Memory Multiprocessors with ILP Processors,” Computer, vol. 35, no. 2, pp. 40-49, Feb. 2002.
[17] S.C. Woo, M. Ohara, E. Torrie, J.P. Singh, and A. Gupta, “The SPLASH-2 Programs: Characterization and Methodological Considerations,” Proc. 22nd Symp. Computer Architecture, pp. 24-36, 1995.
[18] “Comparison between VxWorks/x86 5.3.1, QNX 4.25 and pSOSystem/x86 2.2.6,” Doc No. DSE-RTOS-EVA-011, http:/www. dedicated-systems.com, June 2001.
[19] Seamless CVE, http://www.mentor.comseamless, 2005.
[20] ModelSim, http://www.mentor.com/products/fv/digital_verifi cation modelsim_se, 2005.
[21] MaxSim, http://www.arm.com/products/DevToolsMaxSim.html. , 2005.
[22] ARM Developer Suite, http://www.arm.com/products/Dev ToolsMaxSim.html , 2005.
[23] iPROVE, http://www.dynalith.com/2003iprove.php, 2005.
[24] Reviera, http://www.aldec.com/productsriviera, 2005.
[25] Palladium and Palladium II, http://www.cadence.com/pro ducts/functional_ver/ palladiumIIindex.aspx, 2005.

Index Terms:
Index Terms- Simulation performance, system-level verification, cosimulation, coemulation, heterogeneous simulation environment.
Citation:
Moo-Kyoung Chung, Chong-Min Kyung, "Enhancing Performance of HW/SW Cosimulation and Coemulation by Reducing Communication Overhead," IEEE Transactions on Computers, vol. 55, no. 2, pp. 125-136, Feb. 2006, doi:10.1109/TC.2006.24
Usage of this product signifies your acceptance of the Terms of Use.