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Reducing Jitter in Embedded Systems Employing a Time-Triggered Software Architecture and Dynamic Voltage Scaling
February 2006 (vol. 55 no. 2)
pp. 113-124
ASCII Text
x 
 
Teera Phatrapornnant, Michael J. Pont, "Reducing Jitter in Embedded Systems Employing a Time-Triggered Software Architecture and Dynamic Voltage Scaling," IEEE Transactions on Computers, vol. 55, no. 2, pp. 113-124, February, 2006.
 
 
BibTex
x
 
@article{ 10.1109/TC.2006.29,
author = {Teera Phatrapornnant and Michael J. Pont},
title = {Reducing Jitter in Embedded Systems Employing a Time-Triggered Software Architecture and Dynamic Voltage Scaling},
journal ={IEEE Transactions on Computers},
volume = {55},
number = {2},
issn = {0018-9340},
year = {2006},
pages = {113-124},
doi = {http://doi.ieeecomputersociety.org/10.1109/TC.2006.29},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - JOUR
JO - IEEE Transactions on Computers
TI - Reducing Jitter in Embedded Systems Employing a Time-Triggered Software Architecture and Dynamic Voltage Scaling
IS - 2
SN - 0018-9340
SP113
EP124
EPD - 113-124
A1 - Teera Phatrapornnant,
A1 - Michael J. Pont,
PY - 2006
KW - Index Terms- Low power design
KW - scheduling
KW - real-time systems and embedded systems.
VL - 55
JA - IEEE Transactions on Computers
ER -
 
We have previously demonstrated that use of an appropriate Dynamic Voltage Scaling (DVS) algorithm can lead to a substantial reduction in CPU power consumption in systems employing a time-triggered cooperative (TTC) scheduler. In this paper, we consider the impact that the use of DVS has on the levels of both clock and task jitter in TTC applications. We go on to describe a modified DVS algorithm (TTC-jDVS) which can be used where low jitter is an important design consideration. We then demonstrate the effectiveness of the modified algorithm on a data set made up of artificial tasks and in a realistic case study.

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Index Terms:
Index Terms- Low power design, scheduling, real-time systems and embedded systems.
Citation:
Teera Phatrapornnant, Michael J. Pont, "Reducing Jitter in Embedded Systems Employing a Time-Triggered Software Architecture and Dynamic Voltage Scaling," IEEE Transactions on Computers, vol. 55, no. 2, pp. 113-124, Feb. 2006, doi:10.1109/TC.2006.29
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