The Community for Technology Leaders
RSS Icon
Issue No.12 - December (2005 vol.54)
pp: 1628-1630
This paper presents a new bit-parallel multiplier for the finite field GF(2^m) defined by an irreducible all-one polynomial. In order to reduce the complexity of the multiplier, we introduce a redundant representation and use the well-known multiplication method proposed by Karatsuba. The main idea is to combine the redundant representation and the Karatsuba method to design an efficient bit-parallel multiplier. As a result, the proposed multiplier requires about 25 percent fewer AND/XOR gates than the previously proposed multipliers using an all-one polynomial, while it has almost the same time delay as the previously proposed ones.
Index Terms- Bit-parallel multiplier, redundant representation, finite field arithmetic, AOP, Karatsuba method.
Ku-Young Chang, Dowon Hong, Hyun-Sook Cho, "Low Complexity Bit-Parallel Multiplier for GF(2^m) Defined by All-One Polynomials Using Redundant Representation", IEEE Transactions on Computers, vol.54, no. 12, pp. 1628-1630, December 2005, doi:10.1109/TC.2005.199
10 ms
(Ver 2.0)

Marketing Automation Platform Marketing Automation Tool