This Article 
   
 Share 
   
 Bibliographic References 
   
 Add to: 
 
Digg
Furl
Spurl
Blink
Simpy
Google
Del.icio.us
Y!MyWeb
 
 Search 
   
Aliasing Probability Calculations for Arbitrary Compaction under Independently Selected Random Test Vectors
December 2005 (vol. 54 no. 12)
pp. 1614-1627
This paper discusses a systematic methodology for calculating the exact aliasing probability associated with schemes that use an arbitrary finite-state machine to compact the response of a combinational circuit to a sequence of independently selected, random test input vectors. The proposed approach identifies the strong influence of fault activation probabilities on the probability of aliasing and uses an asymmetric error model to simultaneously track the states of two (fictitious) compactors, one driven by the response of the fault-free combinational circuit and one driven by the response of the faulty combinational circuit. By deriving the overall Markov chain that describes the combined behavior of these two compactors, we are able to calculate the exact aliasing probability for any test sequence length. In particular, for long enough sequences, the probability of aliasing is shown to only depend on the stationary distribution of the Markov chain. The insights provided by our analysis are used to evaluate the testing performance of simple examples of nonlinear compactors and to demonstrate regimes where they exhibit lower aliasing probability than linear compactors with the same number of states. Finally, by establishing connections with previous work that evaluated aliasing probability in linear compactors, our analysis clarifies the role played by the entropy of the stationary distribution of the compactor states.

[1] M.L. Bushnell and V.D. Agrawal, Essentials of Electronic Testing. Boston: Kluwer Academic, 2000.
[2] M. Abramovici, M. Breuer, and D. Friedman, Digital Systems Testing and Testable Design. Piscataway, N.J.: IEEE Press, 1990.
[3] J. Rajski and J. Tyszer, Arithmetic Built-In Self-Test. Upper Saddle River, N.J.: Prentice Hall, 1998.
[4] P.H. Bardell, W.H. McAnney, and J. Savir, Built-In Test for VLSI: Pseudorandom Techniques. New York: John Wiley & Sons, 1987.
[5] T.W. Williams, W. Daehn, M. Gruetzner, and C.W. Starke, “Bounds and Analysis of Aliasing Errors in Linear Feedback Shift Registers,” IEEE Trans. Computer-Aided Design, vol. 7, pp. 75-83, Jan. 1988.
[6] S.M. Reddy, K.K. Saluja, and M.G. Karpovsky, “A Data Compression Technique for Build-In Self-Test,” IEEE Trans. Computers, vol. 37, no. 9, pp. 1151-1156, Sept. 1988.
[7] A. Ivanov and V.K. Agarwal, “An Analysis of the Probabilistic Behavior of Linear Feedback Signature Registers,” IEEE Trans. Computer-Aided Design, vol. 8, pp. 1074-1088, Oct. 1989.
[8] W. Daehn, T.W. Williams, and K.D. Wagner, “Aliasing Errors in Linear Automata Used as Multiple-Input Signature Analyzers,” IBM J. Research and Development, vol. 34, pp. 363-380, Mar.-May 1990.
[9] D.K. Pradhan, S.K. Gupta, and M.G. Karpovsky, “Aliasing Probability for Multiple Input Signature Analyzer,” IEEE Trans. Computers, vol. 39, no. 4, pp. 586-591, Apr. 1990.
[10] K. Iwasaki and F. Arakawa, “An Analysis of the Aliasing Probability of Multiple-Input Signature Registers in the Case of $2m$ -Ary Symmetric Channel,” IEEE Trans. Computer-Aided Design, vol. 9, pp. 427-438, Apr. 1990.
[11] M. Serra, T. Slater, J. Muzio, and D. Miller, “The Analysis of One-Dimensional Linear Cellular Automata and Their Aliasing Properties,” IEEE Trans. Computer-Aided Design, vol. 9, pp. 767-778, July 1990.
[12] M. Damiani, P. Olivo, and B. Ricco, “Analysis and Design of Linear Finite State Machines for Signature Analysis Testing,” IEEE Trans. Computers, vol. 40, no. 9, pp. 1034-1045, Sept. 1991.
[13] D.K. Pradhan and S.K. Gupta, “A New Framework for Designing and Analyzing BIST Techniques and Zero Aliasing Compression,” IEEE Trans. Computers, vol. 40, no. 6, pp. 743-763, June 1991.
[14] M.S. Elsaholy, S.I. Shaheen, and R.H. Seireg, “A Unified Analytical Expression for Aliasing Error Probability Using Single-Input External- and Internal-XOR LFSR,” IEEE Trans. Computers, vol. 47, no. 12, pp. 1414-1417, Dec. 1998.
[15] M.S. Elsaholy, “Exact AEP Model in Signature Analysis Using LCM,” IEE Proc. E: Computers and Digital Techniques, vol. 146, pp. 247-252, Sept. 1999.
[16] D. Xavier, R.C. Aitken, A. Ivanov, and V.K. Agarwal, “Using an Asymmetric Error Model to Study Aliasing in Signature Analysis Registers,” IEEE Trans. Computer-Aided Design, vol. 11, pp. 16-25, Jan. 1992.
[17] N. Saxena and E. McCluskey, “Parallel Signature Analysis Design with Bounds on Aliasing,” IEEE Trans. Computers, vol. 46, no. 4, pp. 425-438, Apr. 1997.
[18] J.P. Hayes, “Transition Count Testing of Combinational Logic Circuits,” IEEE Trans. Computers, vol. 25, no. 6, pp. 613-620, June 1976.
[19] J. Savir, “Syndrome-Testable Design of Combinational Circuits,” IEEE Trans. Computers, vol. 29, no. 6, pp. 442-451, June 1980.
[20] J.P. Robinson and N.R. Saxena, “A Unified View of Test Compression Methods,” IEEE Trans. Computers, vol. 36, no. 1, pp. 94-99, Jan. 1987.
[21] J.P. Robinson and N.R. Saxena, “Simultaneous Signature and Syndrome Compression,” IEEE Trans. Computer-Aided Design, vol. 7, pp. 584-589, May 1988.
[22] S. Pilarski and K. Wiebe, “On Counter-Based Compaction,” Proc. ISCAS 1991, the 1991 IEEE Int'l Symp. Circuits and Systems, vol. 3, pp. 1885-1888, 1991.
[23] J. Rajski and J. Tyszer, “Test Responses Compaction in Accumulators with Rotate Carry Adders,” IEEE Trans. Computer-Aided Design, vol. 12, pp. 531-539, Apr. 1993.
[24] J. Rajski and J. Tyszer, “Accumulator-Based Compaction of Test Responses,” IEEE Trans. Computers, vol. 42, no. 6, pp. 643-650, June 1993.
[25] K. Chakrabarty and J.P. Hayes, “On the Quality of Accumulator-Based Compaction of Test Responses,” IEEE Trans. Computer-Aided Design, vol. 16, pp. 916-922, Aug. 1997.
[26] S. Sastry and A. Majumdar, “Test Efficiency Analysis of Random Self-Test of Sequential Circuits,” IEEE Trans. Computer-Aided Design, vol. 10, pp. 390-398, Mar. 1991.
[27] S. Pilarski, “Comments on `Test Efficiency Analysis of Random Self-Test of Sequential Circuits',” IEEE Trans. Computer-Aided Design, vol. 14, pp. 1044-1045, Aug. 1995.
[28] S. Pilarski, T. Kameda, and A. Ivanov, “Sequential Faults and Aliasing,” IEEE Trans. Computer-Aided Design, vol. 12, pp. 1068-1074, July 1993.
[29] S. Pilarski and K.J. Wiebe, “Counter-Based Compaction: Delay and Stuck-Open Faults,” IEEE Trans. Computers, vol. 44, no. 6, pp. 780-791, June 1995.
[30] G. Edirisooriya and J.P. Robinson, “Performance of Signature Registers in the Presence of Correlated Errors,” IEE Proc. E: Computers and Digital Techniques, vol. 139, pp. 393-400, Sept. 1992.
[31] D. Xavier, R.C. Aitken, A. Ivanov, and V.K. Agarwal, “Experiments on Aliasing in Signature Analysis Registers,” Proc. Int'l Test Conf., pp. 344-354, 1989.
[32] M. Kopec, “Can Nonlinear Compactors Be Better than Linear Ones?” IEEE Trans. Computers, vol. 44, no. 11, pp. 1275-1282, Nov. 1995.
[33] V.D. Agrawal, “An Information Theoretic Approach to Digital Fault Testing,” IEEE Trans. Computers, vol. 30, no. 8, pp. 582-587, Aug. 1981.
[34] J.G. Kemeny, J.L. Snell, and A.W. Knapp, Denumerable Markov Chains. New York: Springer-Verlag, 1976.
[35] P. Bremaud, Markov Chains: Gibbs Fields, Monte Carlo Simulation, and Queues. New York: Springer-Verlag, 1999.
[36] A. Graham, Kronecker Products and Matrix Calculus with Applications. Math. and Its Applications, Chichester, U.K.: Ellis Horwood Ltd., 1981.
[37] G.D. Hachtel, E. Macii, A. Pardo, and F. Somenzi, “Markovian Analysis of Large Finite State Machines,” IEEE Trans. Computer-Aided Design, vol. 15, pp. 1479-1493, Dec. 1996.
[38] S. Meyn and R. Tweedie, Markov Chains and Stochastic Stability. New York: Springer-Verlag, 1993.
[39] P.W. Glynn and D. Ormoneit, “Hoeffding's Inequality for Uniformly Ergodic Markov Chains,” Statistics and Probability Letters, vol. 56, pp. 143-146, 2002.
[40] N. Saxena, P. Franco, and E. McCluskey, “Simple Bounds on Serial Signature Analysis Aliasing for Random Testing,” IEEE Trans. Computers, vol. 41, no. 5, pp. 638-645, May 1992.
[41] E.J. McCluskey, S. Makar, S. Mourad, and K.D. Wagner, “Probability Models for Pseudorandom Test Sequences,” IEEE Trans. Computer-Aided Design, vol. 7, pp. 68-74, Jan. 1988.
[42] F. Brglez, “On Testability Analysis of Combinational Circuits,” Proc. ISCAS 1984, the 1984 IEEE Int'l Symp. Circuits and Systems, pp. 221-225, May 1984.
[43] S.K. Jain and V.D. Agrawal, “Statistical Fault Analysis,” IEEE Design and Test of Computers, vol. 2, no. 1, pp. 38-44, Feb. 1985.
[44] S.C. Seth, L. Pan, and V.D. Agrawal, “PREDICT— Probabilistic Estimation of Digital Circuit Testability,” Proc. 15th Int'l Symp. Fault-Tolerant Computing, Digest of Papers, pp. 220-225, June 1985.
[45] S.C. Seth, V.D. Agrawal, and H. Farhat, “A Statistical Theory of Digital Circuit Testability,” IEEE Trans. Computers, vol. 39, vol. 6, pp. 582-586, Apr. 1990.
[46] H.A. Farhat and H. Saidian, “Testability Profile Estimation of VLSI Circuits from Fault Coverage,” Proc. First Great Lakes Symp. VLSI, pp. 238-242, 1991.
[47] H.A. Farhat and S.G. From, “A Beta Model for Estimating the Testability and Coverage Distributions of a VLSI Circuit,” IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, vol. 12, pp. 550-554, Apr. 1993.
[48] M. Dalpasso, M. Favalli, P. Olivo, and J.P. Teixeira, “Realistic Testability Estimates for CMOS IC's,” Electronics Letters, vol. 30, pp. 1593-1595, Sept. 1994.
[49] H. Farhat, A. Lioy, and M. Poncino, “Computation of Exact Random Pattern Detection Probability,” Proc. IEEE 1993 Custom Integrated Circuit Conf., pp. 26.7.1-26.7.4, 1993.
[50] F. Brglez and H. Fujiwara, “A Neutral Netlist of 10 Combinational Benchmark Circuits and a Target Translator in Fortran,” Proc. ISCAS 1985, the 1985 IEEE Int'l Symp. Circuits and Systems, pp. 663-698, June 1985.
[51] Y. Zorian and V.K. Agarwal, “Optimizing Error Masking in BIST by Output Data Modification,” J. Electronic Testing: Theory and Applications, vol. 1, pp. 59-71, 1990.
[52] H.D. Schnurmann, E. Lindbloom, and R.G. Carpenter, “The Weighted Random Test-Generator,” IEEE Trans. Computers, vol. 24, no. 7, pp. 695-700, July 1975.
[53] F. Siavoshi, “WTPGA: A Novel Weighted Test-Pattern Generation Approach for VLSI Built-In Self Test,” Proc. Int'l Test Conf., pp. 256-262, 1988.
[54] S. Bou-Ghazale and P.N. Marinos, “Testing with Correlated Test Vectors,” Proc. 22nd Int'l Symp. Fault-Tolerant Computing, Digest of Papers, pp. 256-262, 1992.
[55] J. Savir, “Distributed Generation of Weighted Random Patterns,” IEEE Trans. Computers, vol. 48, no. 12, pp. 1364-1368, Dec. 1999.
[56] J. Savir, G.S. Ditlow, and P.H. Bardell, “Random Pattern Testability,” IEEE Trans. Computers, vol. 33, no. 1, pp. 79-89, Jan. 1980.
[57] C.N. Hadjicostis, “Probabilistic Fault Detection in Finite-State Machines Based on State Occupancy Measurements,” Proc. CDC 2002, the 41st IEEE Conf. Decision and Control, vol. 4, pp. 3994-3999, Dec. 2002.
[58] E. Athanasopoulou and C.N. Hadjicostis, “Aliasing Probability Calculations in Testing Sequential Circuits,” Proc. MED 2003, the 11th Mediterranean Conf. Control and Automation, June 2003.

Index Terms:
Index Terms- Aliasing probability, compaction, fault activation probabilities, random testing.
Citation:
Christoforos N. Hadjicostis, "Aliasing Probability Calculations for Arbitrary Compaction under Independently Selected Random Test Vectors," IEEE Transactions on Computers, vol. 54, no. 12, pp. 1614-1627, Dec. 2005, doi:10.1109/TC.2005.189
Usage of this product signifies your acceptance of the Terms of Use.