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An Analysis of the Performance Impact of Wrong-Path Memory References on Out-of-Order and Runahead Execution Processors
December 2005 (vol. 54 no. 12)
pp. 1556-1571
ASCII Text
x 
 
Onur Mutlu, Hyesoon Kim, David N. Armstrong, Yale N. Patt, "An Analysis of the Performance Impact of Wrong-Path Memory References on Out-of-Order and Runahead Execution Processors," IEEE Transactions on Computers, vol. 54, no. 12, pp. 1556-1571, December, 2005.
 
 
BibTex
x
 
@article{ 10.1109/TC.2005.190,
author = {Onur Mutlu and Hyesoon Kim and David N. Armstrong and Yale N. Patt},
title = {An Analysis of the Performance Impact of Wrong-Path Memory References on Out-of-Order and Runahead Execution Processors},
journal ={IEEE Transactions on Computers},
volume = {54},
number = {12},
issn = {0018-9340},
year = {2005},
pages = {1556-1571},
doi = {http://doi.ieeecomputersociety.org/10.1109/TC.2005.190},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - JOUR
JO - IEEE Transactions on Computers
TI - An Analysis of the Performance Impact of Wrong-Path Memory References on Out-of-Order and Runahead Execution Processors
IS - 12
SN - 0018-9340
SP1556
EP1571
EPD - 1556-1571
A1 - Onur Mutlu,
A1 - Hyesoon Kim,
A1 - David N. Armstrong,
A1 - Yale N. Patt,
PY - 2005
KW - Index Terms- Single data stream architectures
KW - speculative execution
KW - runahead execution
KW - processor performance modeling.
VL - 54
JA - IEEE Transactions on Computers
ER -
 
High-performance, out-of-order execution processors spend a significant portion of their execution time on the incorrect program path even though they employ aggressive branch prediction algorithms. Although memory references generated on the wrong path do not change the architectural state of the processor, they affect the arrangement of data in the memory hierarchy. This paper examines the effects of wrong-path memory references on processor performance. It is shown that these references significantly affect the IPC (Instructions Per Cycle) performance of a processor. Not modeling them leads to errors of up to 10 percent (4 percent on average) in IPC estimates for the SPEC CPU2000 integer benchmarks on an out-of-order processor and errors of up to 63 percent on a runahead-execution processor. In general, the error in the IPC increases with increasing memory latency and instruction window size. We find that wrong-path references are usually beneficial for performance because they prefetch data that will be used by later correct-path references. L2 cache pollution is found to be the most significant negative effect of wrong-path references. Code examples are shown to provide insights into how wrong-path references affect performance. We also show that it is crucial to model wrong-path references to accurately estimate the performance improvement provided by runahead execution.

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Index Terms:
Index Terms- Single data stream architectures, speculative execution, runahead execution, processor performance modeling.
Citation:
Onur Mutlu, Hyesoon Kim, David N. Armstrong, Yale N. Patt, "An Analysis of the Performance Impact of Wrong-Path Memory References on Out-of-Order and Runahead Execution Processors," IEEE Transactions on Computers, vol. 54, no. 12, pp. 1556-1571, Dec. 2005, doi:10.1109/TC.2005.190
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