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Synchro-Tokens: A Deterministic GALS Methodology for Chip-Level Debug and Test
December 2005 (vol. 54 no. 12)
pp. 1532-1546
This paper describes a novel deterministic globally-asynchronous locally-synchronous (GALS) methodology called "Synchro-Tokens.” Wrappers around the synchronous blocks keep the system globally asynchronous while ensuring that each transition, although arriving at a nondeterministic time, is sensed by the synchronous block during a deterministic cycle of the local clock. This determinism facilitates debug and test methodologies, such as the use of stored-pattern testers, which are effective only when the system behavior is predictable and repeatable. Applications of Synchro-Tokens to GALS systems with two or more synchronous blocks and one or more asynchronous data channels are shown. Synchro-Tokens supports both pipelined and unpipelined channels and a variety of clock generation methodologies. Novel schematic level designs of the wrapper components in a 180-nm technology are used to compare the performance of several different deterministic GALS design styles.

[1] K. Mohanram and N. Touba, “Eliminating Non-Determinism during Test of High-Speed Source Synchronous Differential Buses,” Proc. 2003 VLSI Test Symp., pp. 121-127, 2003.
[2] F. Gurkaynak, T. Villiger, S. Oetiker, N. Felber, H. Kaeslin, and W. Fichtner, “A Functional Test Methodology for Globally-Asynchronous Locally-Synchronous Systems,” Proc. Eighth Int'l Symp. Asynchronous Circuits and Systems (ASYNC 2002), 2002.
[3] J. Katz and R. Rajsuman, “A New Paradigm in Test for the Next Millenium,” Proc. 2000 Int'l Test Conf., pp 468-476, 2000.
[4] Y. Zorian, E. Marinissen, and S. Dey, “Testing Embedded-Core Based System Chips,” Proc. 1998 Int'l Test Conf., pp 130-143, 1998.
[5] D. Josephson, S. Poehlman, and V. Govan, “Debug Methodology for the McKinley Processor,” Proc. 2001 Int'l Test Conf., pp 451-460, 2001.
[6] F. Rosenberger, C. Molnar, T. Chaney, and T.-P. Fang, “Q-Modules: Internally-Clocked Delay Insensitive Modules,” IEEE Trans. Computers, vol. 37, no. 9, pp. 1005-1018, Sept. 1988.
[7] W.S. VanScheik and R.F. Tinder, “High Speed Externally Asynchronous/Internally Clocked Systems,” IEEE Trans. Computers, vol. 46, no. 7, pp. 824-829, July 1997.
[8] S. Kim and R. Sridhar, “Hierarchical Synchronization Scheme Using Self-Timed Mesochronous Interconnections,” Proc. 1997 IEEE Int'l Symp. Circuits and Systems, pp. 1824-1827, 1997.
[9] W. Lim, “Design Methodology for Stoppable Clock Systems,” IEE Proc., vol. 133, part E, no. 1, pp 65-69, Jan. 1986.
[10] K. Yun and A. Dooply, “Pausible Clocking-Based Heterogeneous Systems,” IEEE Trans. VLSI Systems, vol. 7, no. 4, pp. 482-488, Dec. 1999.
[11] J. Muttersbach, T. Villiger, and W. Fichtner, “Practical Design of Globally-Asynchronous Locally-Synchronous Systems,” Proc. Sixth Int'l Symp. Advanced Research in Asynchronous Circuits and Systems (ASYNC 2000), pp. 52-59, 2000.
[12] M. Heath and I. Harris, “Synchro-Tokens: A Deterministic GALS Architecture,” Proc. Int'l Test Synthesis Workshop (ITSW), 2003.
[13] M. Heath and I. Harris, “A Deterministic Globally-Asynchronous Locally-Synchronous Methodology for Validation, Debug, and Test,” Proc. North Atlantic Test Workshop (NATW), no proceedings published, 2003.
[14] M. Heath and I. Harris, “A Deterministic Globally Asynchronous Locally Synchronous Microprocessor Architecture,” Proc. Fourth Int'l Workshop Microprocessor Test and Verification (MTV), 2003.
[15] M. Heath, W. Burleson, and I. Harris, “Synchro-Tokens: Eliminating Nondeterminism to Enable Chip-Level Test of Globally Asynchronous Locally Synchronous SoC's,” Design Automation and Test in Europe, pp. 410-415, Feb. 2004.
[16] M. Heath, “Synchro-Tokens: A Deterministic Globally Asynchronous Locally Synchronous Architecture,” PhD dissertation, Univ. of Massachusetts at Amherst, May 2004.
[17] J. Kessels, A. Peeters, P. Wielage, and S-J Kim, “Clock Synchronization through Handshake Signalling,” Proc. 2002 Int'l Symp. Advanced Research in Asynchronous Circuits and Systems, pp. 59-68, 2002.
[18] D. Chapiro, “Globally-Asynchronous Locally-Synchronous Systems,” PhD thesis, Stanford Univ., Report No. STAN-CS-84-1026, Oct. 1984.
[19] P. Nilsson and M. Torkelson, “A Monolithic Digital Clock-Generator for On-Chip Clocking of Custom DSP's,” IEEE J. Solid-State Circuits, vol. 31, no. 5, pp. 700-706, May 1996.
[20] I. Sutherland, “Micropipelines,” Comm. ACM, vol. 32, no. 6, pp. 720-738, June 1989.
[21] T. Chelcea and S. Nowick, “Robust Interfaces for Mixed-Timing Systems with Application to Latency-Insensitive Protocols,” Proc. Design Automation Conference (DAC), pp. 21-26, 2001.
[22] M. Greenstreet, “Implementing a STARI Chip,” Proc. 1995 IEEE Int'l Conf. Computer Design, pp. 38-43, 1995.
[23] A. Chakraborty and M.R. Greenstreet, “Efficient Self-Timed Interfaces for Crossing Clock Domains,” Proc. Ninth Int'l Symp. Asynchronous Circuits and Systems (ASYNC 2003), pp. 78-88, 2003.
[24] R. Javagal, A. Datta, and S. Ghosh, “Detecting Deadlocks in Distributed Systems,” Proc. IEEE Int'l Symp. Circuits and Systems, vol. 2, pp. 1013-1016, 1991.
[25] G. Hinton, M. Upton, D. Sager, D. Boggs, D. Carmean, P. Roussel, T. Chappell, T. Fletcher, M. Milshtein, M. Sprague, S. Samaan, and R. Murray, “A 0. 18-mm CMOS IA-32 Processor With a 4-GHz Integer Execution Unit,” IEEE J. Solid State Circuits, vol. 36, no. 11, pp. 1617-1627, Nov. 2001.

Index Terms:
Index Terms- GALS, globally asynchronous locally synchronous, nondeterminism, debug, test, SoC.
Matthew W. Heath, Wayne P. Burleson, Ian G. Harris, "Synchro-Tokens: A Deterministic GALS Methodology for Chip-Level Debug and Test," IEEE Transactions on Computers, vol. 54, no. 12, pp. 1532-1546, Dec. 2005, doi:10.1109/TC.2005.203
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