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Code Size Reduction in Heterogeneous-Connectivity-Based DSPs Using Instruction Set Extensions
October 2005 (vol. 54 no. 10)
pp. 1216-1226
Existing trend of processors shows a progress toward customizable and reconfigurable architectures. In this paper, we study the benefit of combining the architectural design of a VLIW DSP and the concepts of modern customizable processors like ASIPs (Application Specific Instruction Set Processors) for code size reduction. VLIW DSP architectures exhibit heterogeneous connections between functional units and register files for speeding up special tasks. Such architectural characteristics can be effectively exploited through the use of complex instruction set extensions (ISEs). Although VLIWs are increasingly being used for DSP applications to achieve very high performance, such architectures are known to suffer from increased code size. This paper also addresses how to generate and use ISEs that can result in significant code size reduction in VLIW DSPs without degrading performance. Unfortunately, contemporary techniques for generation of ISEs when applied before resource-binding fail to generate legal ISEs for VLIW architectures with heterogeneous connectivity between the functional units and register files. We propose a Heuristic-based approach to generate ISEs for a generalized heterogeneous-connecitivity-based VLIW DSP architecture. We achieve an average code size reduction of 25 percent on the MiBench suite with no penalty in performance by applying our ISE generation algorithms on the TI TMS320C6xx, a representative VLIW DSP. We also show that the overhead of the required architectural assists for our approach is minimal: The TMS320C6xx pipeline meets the required timing with only a limited overhead in area.

[1] TI TMS320C6xx User Manual, http:/www.ti.com, 2005.
[2] Intel Itanium Processor, http://developer.intel.com/design/ itanium manuals.htm, 2005.
[3] S. Hanono and S. Devadas, “Instruction Selection, Resource Allocation and Scheduling in the AVIV Retargetable Code Generator,” Proc. Design Automation Conf., pp. 510-515, 1998.
[4] T.M. Conte, S. Banerjia, S.Y. Larin, K.N. Menezes, and S.W. Sathaye, “Instruction Fetch Mechanisms for VLIW Architectures with Compressed Encodings,” Proc. 29th Int'l Symp. Microarchitecture, pp. 201-211, 1996.
[5] S. Aditya, S.A. Mahlke, and B.R. Rau, “Code Size Minimization and Retargetable Assembly for EPIC and VLIW Instruction Formats,” Technical Report PL-2000-141, HP Labs, 2000.
[6] M. Kozuch and A. Wolfe, “Compression of Embedded System Programs,” Proc. Int'l Conf. Computer Design, pp. 270-277, 1994.
[7] S.Y. Liao, S. Devadas, and K. Keutzer, “Code Density Optimization for Embedded DSP Processors using Data Compression Techniques,” IEEE Trans. Computer Aided Design, vol. 17, no. 7, pp. 601-608, 1998.
[8] H. Zhou and T.M. Conte, “Code Size Efficiency in Global Scheduling for ILP Processors,” Proc Sixth Ann. Workshop Interaction between Compilers and Computer Architectures, 2002.
[9] I.-J. Huang and A.M. Despain, “Generating Instruction Sets and Microarchitectures from Applications,” Proc. Int'l Conf. Computer-Aided Design, 1994.
[10] B.K. Holmer, “A Tool for Processor Instruction Set Design,” Proc. Conf. European Design Automation, 1994.
[11] J.-E. Lee, K. Choi, and N. Dutt, “Efficient Instruction Encoding for Automatic Instruction Set Design of Configurable ASIPs,” Proc. Int'l Conf. Computer Aided Design, 2002.
[12] H. Choi, J.-S. Kim, C.-W. Yoon, I.-C. Park, S.H. Hwang, and C.-M. Kyung, “Synthesis of Application Specific Instructions for Embedded DSP Software,” IEEE Trans. Computers, 1999.
[13] R. Leupers and P. Marwedel, “Instruction Selection for Embedded DSPs with Complex Instructions,” Proc. European Design Automation Conf., 1996.
[14] F. Onion, A. Nicolau, and N. Dutt, “Compiler Feedback in ASIP Design,” Proc. Conf. Design, Automation, and Test in Europe, 1995.
[15] M. Arnold and H. Corporaal, “Instruction Set Synthesis Using Operation Pattern Detection,” Proc. Fifth Ann. Conf. Advanced School for Computing and Imaging, 1999.
[16] F. Sun, S. Ravi, A. Raghunathan, and N.K. Jha, “Synthesis of Custom Processors Based on Extensible Platforms,” Proc. Int'l Conf. Computer Aided Design, 2002.
[17] D. Goodwin and D. Petkov, “Automatic Generation of Application Specific Processors,” Proc. Int'l Conf. Compilers, Architectures, and Synthesis for Embedded Systems, 2003.
[18] K. Atasu, L. Pozzi, and P. Ienne, “Automatic Application-Specific Instruction-Set Extensions under Microarchitectural Constraints,” Proc. Design Automation Conf., 2003.
[19] P. Biswas, S. Banerjee, N. Dutt, L. Pozzi, and P. Ienne, “ISEGEN: Generation of High-Quality Instruction Set Extensions by Iterative Improvement,” Proc. Design, Automation and Test in Europe, 2005.
[20] R.M. Karp, “Reducibility Among Combinatorial Problems,” Complexity of Computer Computations, Plenum Press, 1972.
[21] S.S. Muchnick, Advanced Compiler Design and Implementation. Morgan Kaufmann, 1997.
[22] A. Halambi, P. Grun, V. Ganesh, A. Khare, N. Dutt, and A Nicolau, “EXPRESSION: A Language for Architecture Exploration through Compiler/Simulator Retargetability,” Proc. Conf. Design, Automation and Test in Europe, 1999.
[23] M.R. Guthaus, J.S. Ringenberg, D. Ernst, T.M. Austin, T. Mudge, and R.B. Brown, “MiBench: A Free Commercially Representative Embedded Benchmark Suite,” Proc. IEEE Sixth Ann. Workshop Workload Characterization, http://www.eecs.umich.edu/jringenb mibench /, Dec. 2001.

Index Terms:
Index Terms- Coprocessors, ASIP, VLIW, DSP, instruction set extensions, code size reduction.
Citation:
Partha Biswas, Nikil D. Dutt, "Code Size Reduction in Heterogeneous-Connectivity-Based DSPs Using Instruction Set Extensions," IEEE Transactions on Computers, vol. 54, no. 10, pp. 1216-1226, Oct. 2005, doi:10.1109/TC.2005.157
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