This Article 
   
 Share 
   
 Bibliographic References 
   
 Add to: 
 
Digg
Furl
Spurl
Blink
Simpy
Google
Del.icio.us
Y!MyWeb
 
 Search 
   
Testing from Partial Deterministic FSM Specifications
September 2005 (vol. 54 no. 9)
pp. 1154-1165
This paper addresses the problem of test generation from partially specified deterministic Finite State Machines (FSMs) that may have indistinguishable states and, thus, are not necessarily reduced (minimized). The known methods for checking experiments that are based on state identification are not applicable to unreduced machines. We propose the so-called State-Counting approach that is directly applicable to unreduced FSMs. The approach generalizes the idea of state identification in test generation methods for deterministic machines.

[1] G. v. Bochmann and A. Petrenko, “Protocol Testing: Review of Methods and Relevance for Software Testing,” Proc. ACM Int'l Symp. Software Testing and Analysis (ISSTA '94) pp. 109-124, 1994.
[2] T.S. Chow, “Test Software Design Modeled by Finite State Machines,” IEEE Trans. Software Eng., vol. 4, no. 3, pp. 178-187, 1978.
[3] S. Fujiwara, G. v. Bochmann, F. Khendek, M. Amalou, and A. Ghedamsi, “Test Selection Based on Finite State Models,” IEEE Trans. Software Eng., vol. 17, no. 6, pp. 591-603, June 1991.
[4] S. Goren and F.J. Ferguson, “CHESMIN: A Heuristic for State Reduction in Incompletely Specified Finite State Machines,” Proc. 2002 Design, Automation, and Test in Europe Conf. and Exhibition, 2002.
[5] A. Gill, Introduction to the Theory of Finite-State Machines. New York: McGraw-Hill, 1962.
[6] G. Gonenc, “A Method for the Design of Fault Detection Experiments,” IEEE Trans. Computers, vol. 19, no. 6, pp. 551-558, June 1970.
[7] F.C. Hennie, “Fault Detecting Experiments for Sequential Circuits,” Proc. IEEE Fifth Ann. Symp. Switching Circuit Theory and Logical Design, pp. 95-110, 1964.
[8] R.M. Hierons and H. Ural, “Reduced Length Checking Sequences,” IEEE Trans. Computers, vol. 51, no. 9, pp. 1111-1117, Sept. 2002.
[9] E.P. Hsieh, “Checking Experiments for Sequential Machines,” IEEE Trans. Computers, vol. 20, no. 10, pp. 1152-1166, Oct. 1971.
[10] J. Kella, “Sequential Machine Identification,” IEEE Trans. Computers, vol. 20, no. 3, pp. 332-338, Mar. 1971.
[11] J. Kim and M.M. Newborn, “The Simplification of Sequential Machines with Input Restrictions,” IEEE Trans. Computers, vol. 21, no. 12, pp. 1440-1443, Dec. 1972.
[12] Z. Kohavi, Switching and Finite Automata Theory. New York: McGraw-Hill, 1970.
[13] I. Koufareva and M. Dorofeeva, “A Novel Modification of W-Method,” Joint Bull. Novosibirsk Computing Center and A.P. Ershov Inst. of Informatics Systems, Series: Computing Science, no. 18, pp. 69-81, NCC Publisher, Novosibirsk, 2002.
[14] R. Lai, “A Survey of Communication Protocol Testing,” J. Systems and Software, vol. 62, pp. 21-46, 2002.
[15] D. Lee and M. Yannakakis, “Testing Finite-State Machines: State Identification and Verification,” IEEE Trans. Computers, vol. 43, no. 3, pp. 306-320, Mar. 1994.
[16] D. Lee and M. Yannakakis, “Principles and Methods of Testing Finite State Machines, a Survey,” Proc. IEEE, vol. 84, no. 8, pp. 1090-1123, 1996.
[17] E. Moore, “GedankenExperiments on Sequential Machines,” Automata Studies, Princeton, N.J.: Princeton Univ. Press, pp. 129-153, 1956.
[18] A. Petrenko, “Fault Model-Driven Test Derivation from Finite State Models: Annotated Bibliography,” Proc. Modeling and Verification of Parallel Processes (MOVEP 2000), pp. 196-205, 2000.
[19] A. Petrenko, N. Yevtushenko, and G. v. Bochmann, “Testing Deterministic Implementations from Their Nondeterministic Specifications,” Proc. IFIP Ninth Int'l Workshop Testing of Communicating Systems, pp. 125-140, 1996.
[20] A. Petrenko, N. Yevtushenko, and R. Dssouli, “Testing Strategies for Communicating FSMs,” Proc. IFIP Seventh Int'l Workshop Protocol Test Systems, pp. 193-208, 1994.
[21] A. Petrenko, N. Yevtushenko, A. Lebedev, and A. Das, “Nondeterministic State Machines in Protocol Conformance Testing,” Proc. IFIP Sixth Int'l Workshop Protocol Test Systems, pp. 363-378, 1993.
[22] A. Petrenko and N. Yevtushenko, “On Test Derivation from Partial Specifications,” Proc. IFIP Joint Int'l Conf. Formal Description Techniques for Distributed Systems and Comm. Protocols and Protocol Specification, Testing, and Verification (FORTE/PSTV 2000) pp. 85-102, 2000.
[23] J.F. Poage and E.J. McCluskey, “Derivation of Optimum Test Sequences for Sequential Machines,” Proc. Fifth Ann. Symp. Switching Theory and Logical Design, pp. 121-132, 1964.
[24] I. Pomeranz and S.M. Reddy, “Test Generation for Multiple State-Table Faults in Finite-State Machines,” IEEE Trans. Computers, vol. 46, no. 7, pp. 783-794, July 1997.
[25] A. Rezaki and H. Ural, “Construction of Checking Sequences Based on Characterization Sets,” Computer Comm., vol. 18, pp. 911-920, Dec. 1995.
[26] J.-K. Rho, G. Hachtel, and F. Somentzi, “Don't Care Sequences and the Optimization of Interacting Finite State Machines,” Proc. IEEE Conf. Computer-Aided Design, pp. 414-421, 1991.
[27] R. Shehady and D.P. Siewiorek, “A Method to Automate User Interface Testing Using Variable Finite State Machines,” Proc. 27th Int'l Symp. Fault Tolerant Computing pp. 80-88, 1997.
[28] B.S.W. Schröder, Ordered Sets: An Introduction. Boston: Birkhäuser, 2003.
[29] D.P. Sidhu and T.K. Leung, “Formal Methods for Protocol Testing: A Detailed Study,” IEEE Trans. Software Eng., vol. 15, no. 4, pp. 413-426, Apr. 1989.
[30] H. Ural, “Formal Methods for Test Sequence Generation,” Computer Comm., vol. 15, no. 5, pp. 311-325, 1992.
[31] M.P. Vasilevskii, “Failure Diagnosis of Automata,” Cybernetics, no. 4, pp. 653-665, 1973.
[32] M. Yannakakis and D. Lee, “Testing Finite State Machines: Fault Detection,” J. Computer and System Sciences, vol. 50, pp. 209-227, 1995.
[33] N. Yevtushenko and A. Petrenko, “Synthesis of Test Experiments in Some Classes of Automata,” Automatic Control and Computer Sciences, no. 4, pp. 50-55, 1990.
[34] N. Yevtushenko and A. Petrenko, “Test Derivation Method for an Arbitrary Deterministic Automaton,” Automatic Control and Computer Sciences, no. 5, pp. 65-68, 1990.

Index Terms:
Index Terms- Finite State Machine, partially specified FSM, test generation, weak conformance testing, fault detection, state identification, checking experiment.
Citation:
Alexandre Petrenko, Nina Yevtushenko, "Testing from Partial Deterministic FSM Specifications," IEEE Transactions on Computers, vol. 54, no. 9, pp. 1154-1165, Sept. 2005, doi:10.1109/TC.2005.152
Usage of this product signifies your acceptance of the Terms of Use.