This Article 
   
 Share 
   
 Bibliographic References 
   
 Add to: 
 
Digg
Furl
Spurl
Blink
Simpy
Google
Del.icio.us
Y!MyWeb
 
 Search 
   
Clustered Worst-Case Execution-Time Calculation
September 2005 (vol. 54 no. 9)
pp. 1104-1122
ASCII Text
x 
 
Andreas Ermedahl, Friedhelm Stappert, Jakob Engblom, "Clustered Worst-Case Execution-Time Calculation," IEEE Transactions on Computers, vol. 54, no. 9, pp. 1104-1122, September, 2005.
 
 
BibTex
x
 
@article{ 10.1109/TC.2005.139,
author = {Andreas Ermedahl and Friedhelm Stappert and Jakob Engblom},
title = {Clustered Worst-Case Execution-Time Calculation},
journal ={IEEE Transactions on Computers},
volume = {54},
number = {9},
issn = {0018-9340},
year = {2005},
pages = {1104-1122},
doi = {http://doi.ieeecomputersociety.org/10.1109/TC.2005.139},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - JOUR
JO - IEEE Transactions on Computers
TI - Clustered Worst-Case Execution-Time Calculation
IS - 9
SN - 0018-9340
SP1104
EP1122
EPD - 1104-1122
A1 - Andreas Ermedahl,
A1 - Friedhelm Stappert,
A1 - Jakob Engblom,
PY - 2005
KW - Index Terms- WCET analysis
KW - WCET calculation
KW - hard real-time
KW - embedded systems.
VL - 54
JA - IEEE Transactions on Computers
ER -
 
Knowing the Worst-Case Execution Time (WCET) of a program is necessary when designing and verifying real-time systems. A correct WCET analysis method must take into account the possible program flow, such as loop iterations and function calls, as well as the timing effects of different hardware features, such as caches and pipelines. A critical part of WCET analysis is the calculation, which combines flow information and hardware timing information in order to calculate a program WCET estimate. The type of flow information which a calculation method can take into account highly determines the WCET estimate precision obtainable. Traditionally, we have had a choice between precise methods that perform global calculations with a risk of high computational complexity and local methods that are fast but cannot take into account all types of flow information. This paper presents an innovative hybrid method to handle complex flows with low computational complexity, but still generate safe and tight WCET estimates. The method uses flow information to find the smallest parts of a program that have to be handled as a unit to ensure precision. These units are used to calculate a program WCET estimate in a demand-driven bottom-up manner. The calculation method to use for a unit is not fixed, but could depend on the included flow and program characteristics.

[1] “ASTEC Homepage,” 2005, http:/www.astec.uu.se.
[2] “Vinnova Homepage,” 2005, http:/www.vinnova.se.
[3] N. Audsley, A. Burns, R. Davis, K. Tindell, and A. Wellings, “Fixed Priority Pre-Emptive Scheduling: An Historical Perspective,” Real-Time Systems, vol. 8, nos. 2/3, pp. 129-154, 1995.
[4] L. Casparsson, A. Rajnak, K. Tindell, and P. Malmberg, “VolcanoA Revolution in On-Board Communications,” Volvo Technology Report, vol. 1, pp. 9-19, 1998.
[5] J. Ganssle, “Really Real-Time Systems,” Proc. Embedded Systems Conf. (ESC SF) 2001, Apr. 2001.
[6] R. Kirner and P. Puschner, “Transformation of Path Information for WCET Analysis during Compilation,” Proc. 13th Euromicro Conf. Real-Time Systems, (ECRTS '01), June 2001.
[7] J. Engblom and A. Ermedahl, “Modeling Complex Flows for Worst-Case Execution Time Analysis,” Proc. 21st IEEE Real-Time Systems Symp. (RTSS '00), Nov. 2000.
[8] C. Ferdinand, F. Martin, and R. Wilhelm, “Applying Compiler Techniques to Cache Behavior Prediction,” Proc. ACM SIGPLAN Workshop Languages, Compilers, and Tools for Real-Time Systems (LCT-RTS '97), 1997.
[9] Y.-T.S. Li and S. Malik, “Performance Analysis of Embedded Software Using Implicit Path Enumeration,” Proc. 32nd Design Automation Conf., pp. 456-461, 1995.
[10] J. Gustafsson, B. Lisper, C. Sandberg, and N. Bermudo, “A Tool for Automatic Flow Analysis of C-Programs for WCET Calculation,” Proc. Eighth IEEE Int'l Workshop Object-Oriented Real-Time Dependable Systems (WORDS '03), Jan. 2003.
[11] C. Healy, R. Arnold, F. Müller, D. Whalley, and M. Harmon, “Bounding Pipeline and Instruction Cache Performance,” IEEE Trans. Computers, vol. 48, no. 1, Jan. 1999.
[12] N. Holsti, T. Långbacka, and S. Saarinen, “Worst-Case Execution-Time Analysis for Digital Signal Processors,” Proc. EUSIPCO 2000 Conf. (X European Signal Processing Conf.), Sept. 2000.
[13] T. Lundqvist and P. Stenström, “An Integrated Path and Timing Analysis Method based on Cycle-Level Symbolic Execution,” J. Real-Time Systems, May 2000.
[14] F. Stappert and P. Altenbernd, “Complete Worst-Case Execution Time Analysis of Straight-Line Hard Real-Time Programs,” J. Systems Architecture, vol. 46, no. 4, pp. 339-355, 2000.
[15] R. Heckmann, M. Langenbach, S. Thesing, and R. Wilhelm, “The Influence of Processor Architecture on the Design and the Results of WCET Tools,” IEEE Proc. Real-Time Systems Conf., 2003.
[16] S.-S. Lim, Y.H. Bae, C.T. Jang, B.-D. Rhee, S.L. Min, C.Y. Park, H. Shin, K. Park, and C.S. Ki, “An Accurate Worst-Case Timing Analysis for RISC Processors,” IEEE Trans. Software Eng., vol. 21, no. 7, pp. 593-604, July 1995.
[17] S.-K. Kim, S.L. Min, and R. Ha, “Efficient Worst Case Timing Analysis of Data Caching,” Proc. Second IEEE Real-Time Technology and Applications Symp. (RTAS '96), pp. 230-240, 1996.
[18] R. White, F. Müller, C. Healy, D. Whalley, and M. Harmon, “Timing Analysis for Data Caches and Set-Associative Caches,” Proc. Third IEEE Real-Time Technology and Applications Symp. (RTAS '97), pp. 192-202, June 1997.
[19] A. Colin and I. Puaut, “Worst Case Execution Time Analysis for a Processor with Branch Prediction,” J. Real-Time Systems, vol. 18, nos. 2/3, pp. 249-274, May 2000.
[20] T. Mitra and A. Roychoudhury, “Effects of Branch Prediction on Worst Case Execution Time of Programs,” Technical Report 11-01, Nat'l Univ. of Singapore (NUS), Nov. 2001.
[21] J. Engblom, “Processor Pipelines and Static Worst-Case Execution Time Analysis,” PhD dissertation, Dept. of Information Technology, Uppsala Univ., Uppsala, Sweden, Apr. 2002.
[22] J. Engblom and A. Ermedahl, “Pipeline Timing Analysis Using a Trace-Driven Simulator,” Proc. Sixth Int'l Conf. Real-Time Computing Systems and Applications (RTCSA '99), Dec. 1999.
[23] C. Ferdinand, R. Heckmann, M. Langenbach, F. Martin, M. Schmidt, H. Theiling, S. Thesing, and R. Wilhelm, “Reliable and Precise WCET Determination for a Real-Life Processor,” Proc. First Int'l Workshop Embedded Systems (EMSOFT2000), Oct. 2001.
[24] S.-S. Lim, J.H. Han, J. Kim, and S.L. Min, “A Worst Case Timing Analysis Technique for Multiple-Issue Machines,” Proc. 19th IEEE Real-Time Systems Symp. (RTSS '98), Dec. 1998.
[25] J. Schneider and C. Ferdinand, “Pipeline Behaviour Prediction for Superscalar Processors by Abstract Interpretation,” Proc. SIGPLAN Workshop Languages, Compilers and Tools for Embedded Systems (LCTES '99), May 1999.
[26] S. Petters and G. Färber, “Making Worst-Case Execution Time Analysis for Hard Real-Time Tasks on State of the Art Processors Feasible,” Proc. Sixth Int'l Conf. Real-Time Computing Systems and Applications (RTCSA '99), Dec. 1999.
[27] A. Colin and G. Bernat, “Scope-Tree: A Program Representation for Symbolic Worst-Case Execution Time Analysis,” Proc. 14th Euromicro Conf. Real-Time Systems (ECRTS '02), pp. 50-59, 2002.
[28] F. Stappert, A. Ermedahl, and J. Engblom, “Efficient Longest Executable Path Search for Programs with Complex Flows and Pipeline Effects,” Proc. Fourth Int'l Conf. Compilers, Architecture, and Synthesis for Embedded Systems (CASES '01), Nov. 2001.
[29] P. Puschner and A. Schedl, “Computing Maximum Task Execution Times with Linear Programming Techniques,” technical report, Technische Universität Wien, Institut für Technische Informatik, Apr. 1995.
[30] A. Ermedahl, “A Modular Tool Architecture for Worst-Case Execution Time Analysis,” PhD dissertation, Dept. of Information Technology, Uppsala Univ. Uppsala, Sweden, June 2003.
[31] F. Stappert, “From Low-Level to Model-Based and Constructive Worst-Case Execution Time Analysis,” PhD dissertation, Faculty of Computer Science, Electrical Eng., and Math., Univ. of Paderborn, 2004, C-LAB Publication, vol. 17, Shaker Verlag.
[32] P. Atanassov, R. Kirner, and P. Puschner, “Using Real Hardware to Create an Accurate Timing Model for Execution-Time Analysis,” Proc. IEEE Real-Time Embedded Systems Workshop, Dec. 2001.
[33] NEC Corp, V850E/MS1 32/16-bit Single Chip Microcontroller: Architecture, third ed., Jan. 1999, document no. U12197EJ3V0UM00.
[34] ARM 9TDMI Technical Reference Manual, third ed., ARM Ltd., Mar. 2000, document no. DDI 0180A.
[35] T.H. Cormen, C.E. Leiserson, R.L. Rivest, and C. Stein, Introduction to Algorithms, second ed. MIT Press, 2002.
[36] C. Healy, M. Sjödin, V. Rustagi, and D. Whalley, “Bounding Loop Iterations for Timing Analysis,” Proc. Fourth IEEE Real-Time Technology and Applications Symp. (RTAS '98), June 1998.
[37] M. Berkelaar, lp_solve: (Mixed Integer) Linear Programming Problem Solver, 2004, ftp://ftp.es.ele.tue.nl/publp_solve.
[38] “SICStus Prolog User's Manual,” Swedish Inst. of Computer Science, 1995.
[39] “ILOG CPLEX Homepage,” 2004, http://www.ilog.com/productscplex/.

Index Terms:
Index Terms- WCET analysis, WCET calculation, hard real-time, embedded systems.
Citation:
Andreas Ermedahl, Friedhelm Stappert, Jakob Engblom, "Clustered Worst-Case Execution-Time Calculation," IEEE Transactions on Computers, vol. 54, no. 9, pp. 1104-1122, Sept. 2005, doi:10.1109/TC.2005.139
Usage of this product signifies your acceptance of the Terms of Use.