This Article 
 Bibliographic References 
 Add to: 
High-Speed Multioperand Decimal Adders
August 2005 (vol. 54 no. 8)
pp. 953-963
There is increasing interest in hardware support for decimal arithmetic as a result of recent growth in commercial, financial, and Internet-based applications. Consequently, new specifications for decimal floating-point arithmetic have been added to the draft revision of the IEEE-754 Standard for Floating-Point Arithmetic. This paper introduces and analyzes three techniques for performing fast decimal addition on multiple binary coded decimal (BCD) operands. Two of the techniques speculate BCD correction values and correct intermediate results while adding the input operands. The first speculates over one addition. The second speculates over two additions. The third technique uses a binary carry-save adder tree and produces a binary sum. Combinational logic is then used to correct the sum and determine the carry into the next more significant digit. Multioperand adder designs are constructed and synthesized for four to 16 input operands. Analyses are performed on the synthesis results and the merits of each technique are discussed. Finally, these techniques are compared to several previous techniques for high-speed decimal addition.

[1] M. Hill, N. Jouppi, and G. Sohi, Readings in Computer Architecture. San Francisco: Morgan Kaufmann, 2000.
[2] M.F. Cowlishaw, “Decimal Floating-Point: Algorism for Computers,” Proc. 16th IEEE Symp. Computer Arithmetic, pp. 104-111, June 2003.
[3] Draft IEEE Standard for Floating-Point Arithmetic. New York: IEEE, Inc., 2004, http://754r.ucbtest.orgdrafts.
[4] IEEE Standard for Binary Floating-Point Arithmetic. New York: IEEE Inc., 1985.
[5] P. Parhami, Computer Arithmetic: Algorithms and Hardware Designs. New York: Oxford Univ. Press, 2000.
[6] R.D. Kenney and M.J. Schulte, “Multioperand Decimal Addition,” Proc. IEEE CS Ann. Symp. VLSI, pp. 251-253, Feb. 2004.
[7] R.K. Richards, Arithmetic Operations in Digital Computers. D. Van Nostrand Company, Inc., 1955.
[8] M. Schmookler and A. Weinberger, “High Speed Decimal Addition,” IEEE Trans. Computers, vol. 20, no. 8, pp. 862-867, Aug. 1971.
[9] C.-H. Yeh and B. Parhami, “Efficient Pipelined Multi-Operand Adders with High Throughput and Low Latency: Designs and Applications,” Conf. Record 30th Asilomar Conf. Signals, Systems and Computers, vol. 2, pp. 894-898, Nov. 1996.
[10] P. Kornerup, “Reviewing 4-to-2 Adders for Multi-Operand Addition,” Proc. IEEE Int'l Conf. Application-Specific Systems, Architectures, and Processors, pp. 218-229, July 2002.
[11] C.S. Wallace, “Suggestion for a Fast Multiplier,” IEEE Trans. Electronic Computers, vol. 13, pp. 14-17, 1964.
[12] M.T. Santoro and M.A. Horowitz, “SPIM: A Pipelined 64x64 Bit Iterative Multiplier,” IEEE J. Solid-State Circuits, vol. 24, pp. 487-494, 1989.
[13] H. Schmid, Decimal Computation. John Wiley & Sons, 1974.
[14] M.A. Erle and M.J. Schulte, “Decimal Multiplication via Carry-Save Addition,” Proc. IEEE 14th Int'l Conf. Application-Specific Systems, Architectures, and Processors, pp. 348-358, June 2003.
[15] T. Ohtsuki et al., “Apparatus for Decimal Multiplication,” US Patent #4,677,583, June 1987.
[16] B. Shirazi, D.Y. Yun, and C.N. Zhang, “RBCD: Redundant Binary Coded Decimal Adder,” IEE Proc.— Part E, vol. 136, no. 2, Mar. 1989.
[17] B. Shirazi, D.Y. Yun, and C.N. Zhang, “VLSI Designs for Redundant Binary-Coded Decimal Addition,” Proc. Seventh Ann. Int'l Conf. Computers and Comm., pp. 52-56, Mar. 1988.
[18] W. Bultmann, W. Haller, H. Wetter, and A. Worner Alexander, “Binary and Decimal Adder Unit,” US Patent #6,292,819, Sept. 2001.
[19] J.R. Eaton and K. Hughes, “Decimal Arithmetic Apparatus and Method,” US Patent #5,745,399, Apr. 1998.
[20] S. InSeok, “High-Speed Binary and Decimal Arithmetic Logic Unit,” US Patent #4,866,656, Sept. 1989.
[21] S. Singh, “High-Speed Radix 100 Parallel Adder,” US Patent #6,546,411, Apr. 2003.
[22] W. Haller, U. Krauch, T. Ludwig, and H. Wetter, “Combined Binary/Decimal Adder Unit,” US Patent #6,546,411, July 1999.
[23] M.J. Adiletta and V.C. Lamere, “BCD Adder Circuit,” US Patent #4,805,131, Feb. 1989.
[24] J.L. Anderson, “Binary or BCD Adder with Precorrected Result,” US Patent #4,172,288, Oct. 1979.

Index Terms:
Index Terms- Computer arithmetic, decimal arithmetic, multioperand adders, hardware designs.
Robert D. Kenney, Michael J. Schulte, "High-Speed Multioperand Decimal Adders," IEEE Transactions on Computers, vol. 54, no. 8, pp. 953-963, Aug. 2005, doi:10.1109/TC.2005.129
Usage of this product signifies your acceptance of the Terms of Use.