An Algorithm for Trading Off Quantization Error with Hardware Resources for MATLAB-Based FPGA Design
Issue No.07 - July (2005 vol.54)
Prith Banerjee , IEEE
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/TC.2005.106
Most practical FPGA designs of digital signal processing (DSP) applications are limited to fixed-point arithmetic owing to the cost and complexity of floating-point hardware. While mapping DSP applications onto FPGAs, a DSP algorithm designer must determine the dynamic range and desired precision of input, intermediate, and output signals in a design implementation. The first step in a MATLAB-based hardware design flow is the conversion of the floating-point MATLAB code into a fixed-point version using "quantizers” from the Filter Design and Analysis (FDA) Toolbox for MATLAB. This paper describes an approach to automate the conversion of floating-point MATLAB programs into fixed-point MATLAB programs, for mapping to FPGAs by profiling the expected inputs to estimate errors. Our algorithm attempts to minimize the hardware resources while constraining the quantization error within a specified limit. Experimental results on five MATLAB benchmarks are reported for Xilinx Virtex II FPGAs.
Index Terms- Automation, field programmable gate arrays, fixed-point arithmetic, floating-point arithmetic, quantization.
Sanghamitra Roy, Prith Banerjee, "An Algorithm for Trading Off Quantization Error with Hardware Resources for MATLAB-Based FPGA Design", IEEE Transactions on Computers, vol.54, no. 7, pp. 886-896, July 2005, doi:10.1109/TC.2005.106