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Digit-Recurrence Dividers with Reduced Logical Depth
July 2005 (vol. 54 no. 7)
pp. 837-851
Tom? Lang, IEEE Computer Society
Paolo Montuschi, IEEE Computer Society
Alberto Nannarelli, IEEE Computer Society
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In this paper, we propose a class of division algorithms with the aim of reducing the delay of the selection of the quotient digit by introducing more concurrency and flexibility in its computation. From the proposed class of algorithms, we select one that moves part of the selection function out of the critical path, with a corresponding reduction in the critical path compared with existing alternatives. We present the algorithm and describe the architectures for radix 4 and for radix 16. For radix 16, we use the scheme of overlapping two radix-4 stages. In both cases, radix 4 and radix 16, we show that our algorithms allow the design of units with well-balanced critical paths with consequent decreases of the cycle times. Moreover, in the radix-16 case, we include some additional speculation techniques. To estimate the speedup, we used a rough timing model based on logical effort. For both radices, we estimate a speedup of about 25 percent with respect to previous implementations. In the radix-4 case, this is achieved by using roughly the same area, while, in the radix-16 case, the area is increased by about 30 percent. We verified our estimations by performing a synthesis of the radix-4 units.

[1] M. Ercegovac and T. Lang, Division and Square Root: Digit-Recurrence Algorithms and Implementations. Kluwer Academic, 1994.
[2] M. Ercegovac and T. Lang, Digital Arithmetic. Morgan Kaufmann, 2003.
[3] N. Burgess and C. Hinds, “Design Issues in Radix-4 SRT Square Root and Divide Unit,” Proc. 35th Asilomar Conf. Signals, Systems, and Computers, pp. 1646-1650, Nov. 2001.
[4] D. Harris, S. Oberman, and M. Horowitz, “SRT Division Architectures and Implementations,” Proc. 13th IEEE Symp. Computer Arithmetic, pp. 18-25, 1997.
[5] B. Parhami, “Tight Upper Bounds on the Minimum Precision Required of the Divisor and the Partial Remainder in High-Radix Division,” IEEE Trans. Computers, vol. 52, no. 11, pp. 1509-1514, Nov. 2003.
[6] P. Kornerup, “Revisiting SRT Quotient Digit Selector,” Proc. 16th IEEE Symp. Computer Arithmetic, pp. 38-45, 2003.
[7] E. Rice and R. Hughey, “A New Iterative Structure for Hardware Division: The Parallel Paths Algorithm,” Proc. 16th IEEE Symp. Computer Arithmetic, pp. 54-62, 2003.
[8] G. Gerwig, H. Wetter, E.M. Schwarz, and J. Haess, “High Performance Floating-Point Unit with 116 Bit Wide Divider,” Proc. 16th IEEE Symp. Computer Arithmetic, pp. 87-94, 2003.
[9] I.E. Sutherland, R.F. Sproull, and D. Harris, Logical Effort: Designing Fast CMOS Circuits. Morgan Kaufmann, 1999.
[10] V.G. Oklobdzija et al., “Energy-Delay Estimation Technique for High-Performance Microprocessor VLSI Adders,” Proc. 16th IEEE Symp. Computer Arithmetic, pp. 272-279, 2003.
[11] J.P. Fishburn, “Clock Skew Optimization,” IEEE Trans. Computers, vol. 39, no. 7, pp. 945-951, July 1990.
[12] X. Liu, M.C. Papaefthymiou, and E.G. Friedman, “Retiming and Clock Scheduling for Digital Circuit Optimization,” IEEE Trans. CAD of Integrated Circuits and Systems, vol. 21, no. 2, pp. 184-203, 2002.
[13] E. Antelo, T. Lang, M. Montuschi, and A. Nannarelli, “Fast Radix-4 Retimed Division with Selection by Comparisons,” Proc. IEEE Int'l Conf. Application-Specific Systems, Architectures, and Processors, pp. 185-196, 2002.
[14] A. Nannarelli and T. Lang, “Low-Power Divider,” IEEE Trans. Computers, vol. 48, no. 1, pp. 2-14, Jan. 1999.
[15] E. Antelo, T. Lang, M. Montuschi, and A. Nannarelli, Appendix to “Digit-Recurrence Dividers with Reduced Logical Depth,”, Analysis of the Register Position, Clock Scheduling, and Cycle Time, supplemental material available at archiveshtm, 2005.
[16] M.D. Ercegovac, T. Lang, and P. Montuschi, “Very-High Radix Division with Prescaling and Selection by Rounding,” IEEE Trans. Computers, vol. 43, no 8, pp. 909-918, Aug. 1994.

Index Terms:
Index Terms- Digit-by-digit division, algorithms and architectures for computer arithmetic, division radix 4, division radix 16.
Elisardo Antelo, Tom? Lang, Paolo Montuschi, Alberto Nannarelli, "Digit-Recurrence Dividers with Reduced Logical Depth," IEEE Transactions on Computers, vol. 54, no. 7, pp. 837-851, July 2005, doi:10.1109/TC.2005.115
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