Issue No.07 - July (2005 vol.54)
Robert B. Reese , IEEE
Mitchell Aaron Thornton , IEEE
Cherrice Traver , IEEE
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/TC.2005.105
This paper describes an asynchronous design tool flow known as Phased Logic that converts a clocked design into an asynchronous design implemented as a micropipeline using two-phase control and bundled data signaling. Example designs include variations of a double-precision floating-point clipping operation mapped to two commercial standard cell libraries (0.18µ and 0.13µ) and a five-stage pipelined MIPs-compatible integer unit mapped to the 0.13µ library. The design style includes a feature known as early evaluation, which is a generalized form of bypass, that allows the self-timed design to recover some of the inherent latch delay penalty in micropipelines.
Index Terms- Automatic synthesis, self-timed, asynchronous, pipelined processor, micropipelines.
Robert B. Reese, Mitchell Aaron Thornton, Cherrice Traver, "A Coarse-Grain Phased Logic CPU", IEEE Transactions on Computers, vol.54, no. 7, pp. 788-799, July 2005, doi:10.1109/TC.2005.105