This Article 
 Bibliographic References 
 Add to: 
Design Considerations for Ultra-Low Energy Wireless Microsensor Nodes
June 2005 (vol. 54 no. 6)
pp. 727-740
This tutorial paper examines architectural and circuit design techniques for a microsensor node operating at power levels low enough to enable the use of an energy harvesting source. These requirements place demands on all levels of the design. We propose an architecture for achieving the required ultra-low energy operation and discuss the circuit techniques necessary to implement the system. Dedicated hardware implementations improve the efficiency for specific functionality, and modular partitioning permits fine-grained optimization and power-gating. We describe modeling and operating at the minimum energy point in the subthreshold region for digital circuits. We also examine approaches for improving the energy efficiency of analog components like the transmitter and the ADC. A microsensor node using the techniques we describe can function in an energy-harvesting scenario.

[1] S. Roundy, P. Wright, and J. Rabaey, “A Study of Low Level Vibrations as a Power Source for Wireless Sensor Nodes,” Computer Comm., vol. 26, no. 11, pp. 1131-1144, July 2003.
[2] H. Kulah and K. Najafi, “An Electromagnetic Micro Power Generator For Low-Frequency Environmental Vibrations,” Proc. 17th IEEE Int'l Conf. Micro Electro Mechanical Systems (MEMS), pp. 237-240, Jan. 2004.
[3] S. Meninger et al., “Vibration-to-Electric Energy Conversion,” IEEE Trans. Very Large Scale Integration (VLSI) Systems, vol. 9, no. 1, pp. 64-76, Feb. 2001.
[4] H. Bottner et al., “New Thermoelectric Components Using Microsystem Technologies,” J. Micro Electro Mechanical Systems, vol. 13, no. 3, pp. 414-420, June 2004.
[5] “Panasonic Solar Cell Technical Handbook '98/99,” Aug. 1998.
[6] J.M. Kahn, R.H. Katz, and K.S. J. Pister, “Next Century Challenges: Mobile Networking for 'Smart Dust',” Proc. Mobicom 1999, pp. 271-278, 1999.
[7] J. Rabaey et al., “PicoRadio Supports Ad Hoc Ultra-Low Power Wireless Networking,” Computer, pp. 42-48, July 2000.
[8] A. Wang and A.P. Chandrakasan, “A 180 mV FFT Processor Using Subthreshold Circuit Techniques,” Proc. Int'l Solid-States Circuits Conf. (ISSCC), pp. 292-293, Feb. 2004.
[9] A. Wang, A. Chandrakasan, and S. Kosonocky, “Optimal Supply and Threshold Scaling for Subthreshold CMOS Circuits,” Proc. Symp. VLSI, pp. 5-9, 2002.
[10] J. Burr and A. Peterson, “Ultra Low Power CMOS Technology,” Proc. Third NASA Symp. VLSI Design, pp. 4.2.1-4.2.13, 1991.
[11] B.H. Calhoun and A. Chandrakasan, “Characterizing and Modeling Minimum Energy Operation for Subthreshold Circuits,” Proc. Int'l Symp. Low Power Electronics and Design (ISLPED), Aug. 2004.
[12] K. Osada et al., “SRAM Immunity to Cosmic-Ray-Induced Multierrors Based on Analysis of an Induced Parasitic Bipolar Effect,” IEEE J. Solid State Circuits, vol. 39, no. 5, pp. 827-833, May 2004.
[13] S. Borkar, “Design Challenges of Technology Scaling,” IEEE Micro, vol. 19, no. 4, pp. 23-29, July/Aug. 1999.
[14] S. Mutoh et al., “1-V Power Supply High-Speed Digital Circuit Technology with Multithreshold-Voltage CMOS,” IEEE J. Solid State Circuits, vol. 30, no. 8, Aug. 1995.
[15] J. Kao, S. Narendra, and A. Chandrakasan, “MTCMOS Hierarchical Sizing Based on Mutual Exclusive Discharge Patterns,” Proc. Design Automation Conf. (DAC), 1998.
[16] M. Anis, S. Areibi, and M. Elmasry, “Design and Optimization of Multithreshold CMOS (MTCMOS) Circuits,” IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, vol. 22, no. 10, Oct. 2003.
[17] S. Shigematsu, S. Mutoh, Y. Matsuya, Y. Tanabe, and J. Yamada, “A 1-V High-Speed MTCMOS Circuit Scheme for Power-Down Application Circuits,” IEEE J. Solid State Circuits, vol. 32, no. 6, pp. 861-869, June 1997.
[18] J. Kao and A. Chandrakasan, “MTCMOS Sequential Circuits,” Proc. European Solid State Circuit Conf. (ESSCIRC), 2001.
[19] B. Calhoun, F. Honore, and A. Chandrakasan, “Design Methodology for Fine-Grained Leakage Control in MTCMOS,” Proc. IEEE Int'l Symp. Low Power Electronics and Design (ISLPED), 2003.
[20] R. Swanson and J.D. Meindl, “Ion-Implanted Complimentary MOS Transistors in Low-Voltage Circuits,” IEEE J. Solid State Circuits, vol. 7, no. 2, pp. 146-153, Apr. 1972.
[21] B.H. Calhoun and A. Chandrakasan, “Standby Power Reduction Using Dynamic Voltage Scaling and Canary Flip-Flop Structures,” IEEE J. Solid State Circuits, vol. 39, no. 9, Sept. 2004.
[22] H. Qin, Y. Cao, D. Markovic, A. Vladimirescu, and J. Rabaey, “SRAM Leakage Suppression by Minimizing Standby Supply Voltage,” Proc. Int'l Symp. Quality Electronic Design (ISQED), 2004.
[23] K. Osada, Y. Saitoh, E. Ibe, and K. Ishibashi, “16.7-fA/Cell Tunnel-Leakage-Suppressed 16-Mb SRAM for Handling Cosmic-Ray-Induced Multierrors,” IEEE J. Solid State Circuits, vol. 38, no. 11, Nov. 2003.
[24] F.M. Gardner, Phase Lock Techniques. New York: Wiley, 1979.
[25] S.H. Cho and A.P. Chandrakasan, “6.5GHz CMOS FSK Modulator for Wireless Sensor Applications,” IEEE Symp. VLSI Circuits, pp. 182-185, 2002.
[26] M. Perrott, T. Tewksbury, and C.G. Sodini, “A 27 mW CMOS Fractional-N Synthesizer Using Digital Compensation for 2.5Mb/s GFSK Modulation,” IEEE J. Solid State Circuits, vol. 32, no. 12, pp. 2048-2060, Dec. 1997.
[27] D.A. Hitko, T.L. Tewksbury, and C.G. Sodini, “A 1 V, 5 mW, 1.8 GHz, Balanced Voltage-Controlled Oscillator with an Integrated Resonator,” Proc. IEEE Intl Symp. Low Power Electronic Design (ISLPED), pp. 46-51, Aug. 1997.
[28] N. Filiol et al., “A 22 mW Bluetooth RF Transceiver with Direct RF Modulation and On-Chip IF Filtering,” Int'l Solid State Circuits Conf. Digest of Technical Papers, pp. 202-203, 2001.
[29] L. Kleinrock, “On Giant Stepping in Packet Radio Networks,” Packet Radio Temporary Note #5 PRT 136, Univ. of California Los Angeles, Mar. 1975.
[30] M. Bhardwaj, T. Garnett, and A. Chandrakasan, “Upper Bounds on the Lifetime of Sensor Networks,” Proc. IEEE Int'l Conf. Comm., pp. 785-790, 2001.
[31] M. Bhardwaj, R. Min, and A. Chandrakasan, “Quantifying and Enhancing Power-Awareness of VLSI Systems,” IEEE Trans. VLSI Systems, pp 757-772, Dec. 2001.
[32] H.-S. Lee, D.A. Hodges, and P.R. Gray, “A Self-Calibrating 15 Bit CMOS A/D Converter,” IEEE J. Solid State Circuits, vol. 19, no. 6, pp. 813-819, Dec. 1984.
[33] G. Promitzer, “12-Bit Low-Power Fully Differential Switched Capacitor Noncalibrating Successive Approiximation ADC with 1MS/s,” IEEE J. Solid State Circuits, vol. 36, no. 7, pp. 1138-1143, July 2001.
[34] R.H. Walden, “Analog-to-Digital Converter Survey and Analysis,” IEEE J. Selected Areas in Comm., vol. 17, no. 4, pp. 539-550, Apr. 1999.
[35] K. Gulati and H.-S. Lee, “A Low-Power Reconfigurable Analog-to-Digital Converter,” IEEE J. Solid State Circuits, vol. 36, no. 12, pp. 1900-1911, Dec. 2001.

Index Terms:
Integrated circuits, energy-aware systems, low-power design, wireless sensor networks.
Benton H. Calhoun, Denis C. Daly, Naveen Verma, Daniel F. Finchelstein, David D. Wentzloff, Alice Wang, Seong-Hwan Cho, Anantha P. Chandrakasan, "Design Considerations for Ultra-Low Energy Wireless Microsensor Nodes," IEEE Transactions on Computers, vol. 54, no. 6, pp. 727-740, June 2005, doi:10.1109/TC.2005.98
Usage of this product signifies your acceptance of the Terms of Use.