Issue No.04 - April (2005 vol.54)
Haridimos T. Vergos , IEEE
Dimitris Nikolos , IEEE
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/TC.2005.63
In this work, we propose a new algorithm for designing diminished-1 modulo 2^n+1 multipliers. The implementation of the proposed algorithm requires n+3 partial products that are reduced by a tree architecture into two summands, which are finally added by a diminished-1 modulo 2^n+1 adder. The proposed multipliers, compared to existing implementations, offer enhanced operation speed and their regular structure allows efficient VLSI implementations.
Modulo 2^n+1 multipliers, computer arithmetic, residue number system, Fermat number transform, VLSI design.
Costas Efstathiou, Haridimos T. Vergos, Giorgos Dimitrakopoulos, Dimitris Nikolos, "Efficient Diminished-1 Modulo 2^n+1 Multipliers", IEEE Transactions on Computers, vol.54, no. 4, pp. 491-496, April 2005, doi:10.1109/TC.2005.63