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Test Vector Embedding into Accumulator-Generated Sequences: A Linear-Time Solution
April 2005 (vol. 54 no. 4)
pp. 476-484
The test set embedding problem is typically formed as follows: Given an n-stage pattern generator and a test set, calculate the minimum number of steps that the generator needs to operate in order to generate all vectors in the test set. The cornerstone of a test set embedding technique is its embedding algorithm. An embedding algorithm, given an n-stage pattern generator initialized to a starting value and an n-bit target vector V, calculates the location of V in the generated sequence. In this paper, a novel algorithm is presented that calculates the location of a vector into a sequence generated by an n-stage accumulator accumulating a constant pattern. The time complexity of the algorithm is of the order {\bf O}{\rm (n)}. To the best of our knowledge, this is the first embedding algorithm of the order {\bf O}{\rm (n)} that has been presented in the literature. Experiments performed on well-known benchmark circuits reveal that complete test sets are embedded in sequences of practically acceptable length.

[1] M. Abramovici, M. Breuer, and A. Freidman, Digital Systems Testing and Testable Design. Computer Science Press, 1990.
[2] P. Bardell, W. McAnney, and J. Savir, Built-In Test for VLSI: Pseudorandom Techniques. John Wiley and Sons, 1987.
[3] C. Dufaza and G. Gambon, “LFSR-Based Deterministic and Pseudorandom Test Pattern Generator Structures,” Proc. European Test Conf., pp. 27-34, 1991.
[4] P.D. Hortensius, R.D. McLeod, W Pries, D. Miller, and H.C. Card, “Cellular Automata-Based Pseudorandom Number Generator for Built-In Self-Test,” IEEE Trans. Computer-Aided Design, vol. 8, no 8, pp. 842-858, Aug. 1986.
[5] A. Stroele, “A Self Test Approach Using Accumulators as Test Pattern Generators,” Proc. Int'l Symp. Circuits and Systems, pp. 2120-2123, 1995.
[6] M. Lempel, S. Gupta, and A. Breuer, “Test Embedding with Discrete Logarithms,” IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, vol. 14, no 5, May 1995.
[7] S. Boubezari and B. Kaminska, “A Deterministic BIST Generator Based on Cellular Automata Structures,” IEEE Trans. Computers, vol. 44, no 6, June 1995.
[8] J. van Sas, F. Catthoor, and H. De Man, “Cellular Automata Based Deterministic Self Test Strategies for Programmable Data Paths,” IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, vol. 13, no. 7, July 1994.
[9] D. Kagaris, S. Tragoudas, and A. Majumdar, “On the Use of Counters for Reproducing Deterministic Test Sets,” IEEE Trans. Computers, vol. 45, no. 12, Dec. 1996.
[10] D. Kagaris and S. Tragoudas, “On the Design of Optimal Counter-Based Schemes for Test Set Embedding,” IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, vol. 18, no. 2, Feb. 1999.
[11] A. Gupta, J. Rajski, and J. Tyszer, “Arithmetic Additive Generators of Pseudo-Exhaustive Test Patterns,” IEEE Trans. Computers, vol. 45, no 8, pp. 939-949, Aug. 1996.
[12] A. Stroele, “Bit Serial Pattern Generation and Response Compaction Using Arithmetic Functions,” Proc. VLSI Test Symp., 1998.
[13] A. Stroele, “BIST Patter Generators Using Addition and Subtraction Operations,” J. Electronic Testing: Theory and Applications, vol. 11, pp. 69-80, 1997.
[14] R. Dorsch and H. Wunderlich, “Accumulator-Based Deterministic BIST,” Proc. Int'l Test Conf., pp. 412-421, 1998.
[15] D. Coppersmith, “Fast Evaluation of Logarithms in Fields of Characteristic Two,” IEEE Trans. Information Theory, pp. 587-594, July 1984.
[16] S. Pohligg and M. Hellman, “An Improved Algorithm for Computing Logarithms over GF(p) and Its Cryptographic Significance,” IEEE Trans. Information Theory, pp. 106-110, Jan. 1978.
[17] R. Bryant, “Graph-Based Algorithms for Boolean Function Manipulation,” IEEE Trans. Computers, vol. 35, no 8, Aug. 1986.
[18] S. Akers, “Binary Decision Diagrams,” IEEE Trans. Computers, vol. 27, no 6, June. 1978.
[19] A. Stroele and F. Mayer, “Methods to Reduce Test Application Time for Accumulator-Based Self Test,” Proc. VLSI Test Symp., pp. 48-53, 1997.
[20] I. Pomeranz and S.M. Reddy, “Sequence to Improve the Levels of Compaction Achievable by Static Compression Techniques,” Proc. Design Automation and Test in Europe (DATE 2001), pp. 214-220, 2001.
[21] I. Pomeranz, L.N. Reddy, and S.M. Reddy, “COMPACTEST: A Method to Generate Compact Test Sets for Combinational Circuits,” Proc. 1991 Int'l Test Conf., pp. 194-203, Oct. 1991.
[22] H. Fujiwara and T. Shimono, “On the Acceleration of Test Generation Algorithms,” IEEE Trans. Computers, vol. 32, no 12, pp. 1137-1144, Dec. 1983.
[23] F. Brglez and H. Fujiwara, “A Neutral Netlist of 10 Combinational Benchmarks Circuits and a Target Translator in FORTRAN,” Proc. Int'l Symp. Circuits and Systems, 1985.

Index Terms:
Built-in self-test, test set embedding, accumulator-based test pattern generation.
Citation:
Ioannis Voyiatzis, "Test Vector Embedding into Accumulator-Generated Sequences: A Linear-Time Solution," IEEE Transactions on Computers, vol. 54, no. 4, pp. 476-484, April 2005, doi:10.1109/TC.2005.69
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