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Issue No.04 - April (2005 vol.54)
pp: 449-460
ABSTRACT
Dual-rail encoding, return-to-spacer protocol, and hazard-free logic can be used to resist power analysis attacks by making energy consumed per clock cycle independent of processed data. Standard dual-rail logic uses a protocol with a single spacer, e.g., all-zeros, which gives rise to energy balancing problems. We address these problems by incorporating two spacers; the spacers alternate between adjacent clock cycles. This guarantees that all gates switch in every clock cycle regardless of the transmitted data values. To generate these dual-rail circuits, an automated tool has been developed. It is capable of converting synchronous netlists into dual-rail circuits and it is interfaced to industry CAD tools. Dual-rail and single-rail benchmarks based upon the Advanced Encryption Standard (AES) have been simulated and compared in order to evaluate the method and the tool.
INDEX TERMS
Alternating spacer protocol, cryptography, design automation, dual-rail encoding, hardware security, hazard-free design, power analysis.
CITATION
Danil Sokolov, Julian Murphy, Alexander Bystrov, Alex Yakovlev, "Design and Analysis of Dual-Rail Circuits for Security Applications", IEEE Transactions on Computers, vol.54, no. 4, pp. 449-460, April 2005, doi:10.1109/TC.2005.61
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