This Article 
 Bibliographic References 
 Add to: 
Design and Analysis of Dual-Rail Circuits for Security Applications
April 2005 (vol. 54 no. 4)
pp. 449-460
Dual-rail encoding, return-to-spacer protocol, and hazard-free logic can be used to resist power analysis attacks by making energy consumed per clock cycle independent of processed data. Standard dual-rail logic uses a protocol with a single spacer, e.g., all-zeros, which gives rise to energy balancing problems. We address these problems by incorporating two spacers; the spacers alternate between adjacent clock cycles. This guarantees that all gates switch in every clock cycle regardless of the transmitted data values. To generate these dual-rail circuits, an automated tool has been developed. It is capable of converting synchronous netlists into dual-rail circuits and it is interfaced to industry CAD tools. Dual-rail and single-rail benchmarks based upon the Advanced Encryption Standard (AES) have been simulated and compared in order to evaluate the method and the tool.

[1] P. Kocher, J. Jaffe, and B. Jun, “Differential Power Analysis,” Proc. Crypto, 1999.
[2] T. Messerges, E. Dabbish, and R. Sloan, “Examining Smart-Card Security under the Threat of Power Analysis Attacks,” IEEE Trans. Computers, vol. 51, no. 5, pp. 541-552, May 2002.
[3] H. Saputra, N. Vijaykrishnan, M. Kandemir, M.J. Irwin, R. Brooks, S. Kim, and W. Zhang, “Masking the Energy Behaviour of DES Encryption,” Proc. Design and Test in Europe Conf. (DATE), 2003.
[4] S. Guilley, P. Hoogvorst, Y. Mathieu, R. Pacalet, and J. Provost, “CMOS Structures Suitable for Secured Hardware,” Proc. Design and Test in Europe Conf. (DATE), pp. 1414-1415, 2004.
[5] K. Tiri, M. Akmal, and I. Verbauwhede, “A Dynamic and Differential CMOS Logic with Signal Independent Power Consumption to Withstand Differential Power Analysis on Smart Cards,” Proc. European Solid-State Circuits Conf. (ESSCIRC), 2002.
[6] S. Moore, R. Anderson, P. Cunningham, R. Mullins, and G. Taylor, “Improving Smart Card Security Using Self-Timed Circuits,” Proc. Int'l Symp. Asynchronous Circuits and Systems (ASYNC), pp. 211-218, 2002.
[7] Z. Yu, S. Furber, and L. Plana, “An Investigation into the Security of Self-Timed Circuits,” Proc. Int'l Symp. Asynchronous Circuits and Systems (ASYNC), pp. 206-215, 2003.
[8] K. Tiri and I. Verbauwhede, “A Logical Level Design Methodology for a Secure DPA Resistant ASIC or FPGA Implementation,” Proc. Design and Test in Europe Conf. (DATE), 2004.
[9] A. Kondratyev and K. Lwin, “Design of Asynchronous Circuits Using Synchronous CAD Tools,” Proc. Design Automation Conf., pp. 107-117, 2002.
[10] L. Plana, P. Riocreux, W. Bardsley, J. Garside, and S. Temple, “SPA— A Synthesisable Amulet Core for Smartcard Applications,” Proc. Int'l Symp. Asynchronous Circuits and Systems (ASYNC), pp. 201-210, 2002.
[11] J. Sparso and S. Furbe, Principles of Asynchronous Circuit Design. Kluwer Academic, 2001.
[12] Self-Timed Control Of Concurrent Processes, V. Varshavsky, ed. Kluwer, 1990 Russian ed., 1986.
[13] I. David, R. Ginosar, and M. Yoeli, “An Efficient Implementation of Boolean Functions as Self-Timed Circuits,” IEEE Trans. Computers, vol. 41, no. 1, pp. 2-11, Jan. 1992.
[14] K. Fant and S. Brandt, “Null Convention Logic: A Complete and Consistent Logic for Asynchronous Digital Circuit Synthesis,” Proc. Int'l Conf. Application-Specific Systems, Architectures and Processors (ASAP), pp. 261-273, 1996.
[15] D. Sokolov, J. Murphy, A. Bystrov, and A. Yakovlev, “Improving the Security of Dual-Rail Circuits,” Proc. Workshop Cryptographic Hardware and Embedded Systems (CHES), 2004.
[16] A. Bystrov, D. Sokolov, A. Yakovlev, and A. Koelmans, “Balancing Power Signature in Secure Systems,” Proc. 14th UK Asynchronous Forum, 2003.
[17] Nat'l Inst. of Standards and Tech nology, “Federal Information Processing Standard 197, The Advanced Encryption Standard (AES),” fips197. pdf, 2001.
[18] J. Daemen and V. Rijmen, The Design of Rijndael. Springer-Verlag, 2002.
[19] R. Usselmann, “Advanced Encryption Standard/Rijndael IP Core,” http:/, 2004.
[20] S. Mangard, M. Aigner, and S. Dominikus, “A Highly Regular and Scalable AES Hardware Architecture,” IEEE Trans. Computers, vol. 52, no. 4, pp. 483-491, Apr. 2003.
[21] J. Wolkerstorfer, E. Oswald, and M. Lamberger, “An ASIC Implementation of AES S-Boxes,” Proc. RSA, 2002.
[22] W. Bainbridge and S. Furber, “Delay Insensitive System-on-Chip Interconnect Using 1-of-4 Data Encoding,” Proc. Int'l Symp. Asynchronous Circuits and Systems (ASYNC), 2001.

Index Terms:
Alternating spacer protocol, cryptography, design automation, dual-rail encoding, hardware security, hazard-free design, power analysis.
Danil Sokolov, Julian Murphy, Alexander Bystrov, Alex Yakovlev, "Design and Analysis of Dual-Rail Circuits for Security Applications," IEEE Transactions on Computers, vol. 54, no. 4, pp. 449-460, April 2005, doi:10.1109/TC.2005.61
Usage of this product signifies your acceptance of the Terms of Use.