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A Class of Unidirectional Bit Serial Systolic Architectures for Multiplicative Inversion and Division over {\rm GF}(2^m)
March 2005 (vol. 54 no. 3)
pp. 370-380
A class of universal unidirectional bit serial systolic architectures for multiplicative inversion and division over Galois field {\rm GF}(2^m) is presented. The field elements are represented with polynomial (standard) basis. These systolic architectures have no carry propagation structures and are suitable for hardware implementations where the dimension of the field is large and may vary. This is the typical case for cryptographic applications. These architectures are independent of any defining irreducible polynomial of a given degree as well. The time complexity is constant and area complexity is linear (w.r.t. field dimension) and these measures are equivalent to or exceed similar proposed designs.

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Index Terms:
Division, extended Euclidean algorithm, finite fields, field arithmetic, inversion, systolic arrays.
Citation:
Amir K. Daneshbeh, M. Anwar Hasan, "A Class of Unidirectional Bit Serial Systolic Architectures for Multiplicative Inversion and Division over {\rm GF}(2^m)," IEEE Transactions on Computers, vol. 54, no. 3, pp. 370-380, March 2005, doi:10.1109/TC.2005.35
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