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Architecture and Implementation of a Vector/SIMD Multiply-Accumulate Unit
March 2005 (vol. 54 no. 3)
pp. 284-293
ASCII Text
x 
 
Albert Danysh, Dimitri Tan, "Architecture and Implementation of a Vector/SIMD Multiply-Accumulate Unit," IEEE Transactions on Computers, vol. 54, no. 3, pp. 284-293, March, 2005.
 
 
BibTex
x
 
@article{ 10.1109/TC.2005.41,
author = {Albert Danysh and Dimitri Tan},
title = {Architecture and Implementation of a Vector/SIMD Multiply-Accumulate Unit},
journal ={IEEE Transactions on Computers},
volume = {54},
number = {3},
issn = {0018-9340},
year = {2005},
pages = {284-293},
doi = {http://doi.ieeecomputersociety.org/10.1109/TC.2005.41},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - JOUR
JO - IEEE Transactions on Computers
TI - Architecture and Implementation of a Vector/SIMD Multiply-Accumulate Unit
IS - 3
SN - 0018-9340
SP284
EP293
EPD - 284-293
A1 - Albert Danysh,
A1 - Dimitri Tan,
PY - 2005
KW - Parallel
KW - high-speed arithmetic
KW - multimedia
KW - data-path design
KW - VLSI
KW - MAC
KW - multiply-accumulate
KW - multiplier
KW - vector
KW - SIMD
KW - Booth
KW - Wallace
KW - signed
KW - unsigned
KW - integer
KW - fixed-point.
VL - 54
JA - IEEE Transactions on Computers
ER -
 
This paper presents a 64-bit fixed-point vector multiply-accumulator (MAC) architecture capable of supporting multiple precisions. The vector MAC can perform one 64\times64, two 32\times32, four 16\times16, or eight 8\times8 bit signed/unsigned multiply-accumulates using essentially the same hardware as a scalar 64-bit MAC and with only a small increase in delay. The scalar MAC architecture is "vectorized” by inserting mode-dependent multiplexing into the partial product generation and by inserting mode-dependent kills in the carry chain of the reduction tree and the final carry-propagate adder. This is an example of "shared segmentation” in which the existing scalar structure is segmented and then shared between vector modes. The vector MAC is area efficient and can be fully pipelined, which makes it suitable for high-performance processors and, possibly, dynamically reconfigurable processors. The "shared segmentation” method is compared to an alternative method, referred to as the "shared subtree” method, by implementing vector MAC designs using two different technologies and three different vector widths.

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Index Terms:
Parallel, high-speed arithmetic, multimedia, data-path design, VLSI, MAC, multiply-accumulate, multiplier, vector, SIMD, Booth, Wallace, signed, unsigned, integer, fixed-point.
Citation:
Albert Danysh, Dimitri Tan, "Architecture and Implementation of a Vector/SIMD Multiply-Accumulate Unit," IEEE Transactions on Computers, vol. 54, no. 3, pp. 284-293, March 2005, doi:10.1109/TC.2005.41
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