This Article 
   
 Share 
   
 Bibliographic References 
   
 Add to: 
 
Digg
Furl
Spurl
Blink
Simpy
Google
Del.icio.us
Y!MyWeb
 
 Search 
   
Addition Related Arithmetic Operations via Controlled Transport of Charge
March 2005 (vol. 54 no. 3)
pp. 243-256
This paper investigates the Single Electron Tunneling (SET) technology-based computation of basic addition related arithmetic functions, e.g., addition and multiplication, via a novel computation paradigm, which we refer to as electron counting arithmetic, that is based on controlling the transport of discrete quantities of electrons within the SET circuit. First, assuming that the number of controllable electrons within the system is unrestricted, we prove that the addition of two n{\hbox{-}}{\rm bit} operands can be computed with a depth-2 network composed out of 3n+1 circuit elements and that the multiplication of two n{\hbox{-}}{\rm bit} operands can be computed with a depth-3 network composed out of 4n-1 circuit elements. Second, assuming that the number of controllable electrons cannot be higher than a given constant r determined by practical limitations, we prove that the addition of two n{\hbox{-}}{\rm bit} operands can be computed with a {\rm depth}{\hbox{-}}\left ({\frac{n}{r}}+3 \right ) network composed out of 3n+1 + {\frac{n}{r}} circuit elements. Under the same restriction, we suggest methods to reduce the addition network depth in the order of \log{{\frac{n}{r}}} and to perform n{\hbox{-}}{\rm bit} multiplication in an O(\log{{\frac{n}{r}}}) delay. Finally, we propose SET-based implementations for a set of basic electron counting building blocks and implement a number of circuits operating under the electron counting paradigm as follows: 4-bit Digital to Analog Converter, 5-bit Analog to Digital Converter, 4-bit adder, and 3-bit multiplier. All proposed implementations are verified by means of simulation.

[1] Y. Taur, D. Buchanan, W. Chen, D. Frank, K. Ismail, S. Lo, G. Sai-Halasz, R. Viswanathan, H. Wann, S. Wind, and H. Wong, “CMOS Scaling into the Nanometer Regime,” Proc. IEEE, vol. 85, no. 4, pp. 486-504, 1997.
[2] “Technology Roadmap for Nanoelectronics,” http://www. cordis.lu/esprit/srcmelna-rm.htm , 1999, published on the internet by the Microelectronics Advanced Research Initiative (MELARI NANO), a European Commission (EC) Information Soc. Technologies (IST) program on Future and Emerging Tech nologies.
[3] K. Likharev, “Single-Electron Devices and Their Applications,” Proc. IEEE, vol. 87, no. 4, pp. 606-632, Apr. 1999.
[4] Y. Ono, Y. Takahashi, K. Yamazaki, M. Nagase, H. Namatsu, K. Kurihara, and K. Murase, “Fabrication Method for IC-Oriented Si Single-Electron Transistors,” IEEE Trans. Electron Devices, vol. 49, no. 3, pp. 193-207, Mar. 2000.
[5] C. Wasshuber, “About Single-Electron Devices and Circuits,” PhD dissertation, TU Vienna, 1998.
[6] C. Heij and J.M.P. Hadley, “A Single-Electron Inverter,” Applied Physics Letters, vol. 78, no. 8, pp. 1140-1142, Feb. 2001.
[7] K. Ishibashi, D. Tsuya, M. Suzuki, and Y. Aoyagi, “Fabrication of a Single-Electron Inverter in Multiwall Carbon Nanotubes,” Applied Physics Letters, vol. 82, no. 19, pp. 3307-3309, Feb. 2001.
[8] D. Averin and A. Odintsov, “Macroscopic Quantum Tunneling of the Electric Charge in Small Tunnel Junctions,” Physics Letters A, vol. 140, no. 5, pp. 251-257, Sept. 1989.
[9] D. Averin and Y. Nazarov, “Virtual Electron Diffusion during Quantum Tunneling of the Electric Charge,” Physical Rev. Letters, vol. 65, no. 19, pp. 2446-2449, Nov. 1990.
[10] S. Lotkhov, H. Zangerle, A. Zorin, and J. Niemeyer, “Storage Capabilities of a Four-Junction Single-Electron Trap with an On-Chip Resistor,” Applied Physics Letters, vol. 75, no. 17, pp. 2665-2667, Oct. 1999.
[11] A. Zorin, S. Lotkhov, H. Zangerle, and J. Niemeyer, “Coulomb Blockade and Cotunneling in Single Electron Circuits with On-Chip Resistors: Towards the Implementation of the R Pump,” J. Applied Physics, vol. 88, no. 5, pp. 2665-2670, Sept. 2000.
[12] S. Lotkhov, S. Bogoslovsky, A. Zorin, and J. Niemeyer, “Operation of a Three-Junction Single-Electron Pump with On-Chip Resistors,” Applied Physics Letters, vol. 78, no. 7, pp. 946-948, Feb. 2001.
[13] K. Likharev, “Correlated Discrete Transfer of Single Electrons in Ultrasmall Tunnel Junctions,” IBM J. Research and Development, vol. 32, no. 1, pp. 144-158, Jan. 1988.
[14] J. Tucker, “Complementary Digital Logic Based on the 'Coulomb Blockade',” J. Applied Physics, vol. 72, no. 9, pp. 4399-4413, Nov. 1992.
[15] R. Chen, A. Korotkov, and K. Likharev, “Single-Electron Transistor Logic,” Applied Physics Letters, vol. 68, no. 14, pp. 1954-1956, Apr. 1996.
[16] N. Yoshikawa, Y. Jinguu, H. Ishibashi, and M. Sugahara, “Complementary Digital Logic Using Resistively Coupled Single- Electron Transistor,” Japanese J. Applied Physics, vol. 35, no. 2B, pp. 1140-1145, Feb. 1996.
[17] M. Jeong, Y. Jeong, S. Hwang, and D. Kim, “Performance of Single-Electron Transistor Logic Composed of Multi-Gate Single-Electron Transistors,” Japanese J. Applied Physics, vol. 36, no. 11, pp. 6706-6710, Nov. 1997.
[18] K. Likharev and V. Semenov, “Possible Logic Circuits Based on the Correlated Single-Electron Tunneling in Ultrasmall Junctions,” Extended Abstracts, Int'l Superconductive Conf., p. 182, 1987.
[19] Y.N. Nazarov and S.V. Vyshenskii, “SET Circuits for Digital Applications,” Single-Electron Tunneling and Mesoscopic Devices, H. Koch and H. Lubbig, eds., vol. 31, pp. 61-66, Springer-Verlag, 1992.
[20] C. Lageweg, S. Cotofana, and S. Vassiliadis, “Static Buffered SET Based Logic Gates,” Proc. Second IEEE Conf. Nanotechnology (NANO), pp. 491-494, Aug. 2002.
[21] C. Lageweg, S. Cotofana, and S. Vassiliadis, “Single Electron Encoded Latches and Flip-Flops,” IEEE Trans. Nanotechnology, vol. 3, no. 2, pp. 237-248, June 2004.
[22] S. Cotofana, C. Lageweg, and S. Vassiliadis, “On Computing Addition Related Arithmetic Operations via Controlled Transport of Charge,” Proc. 16th IEEE Symp. Computer Arithmetic, pp. 245-252, June 2003.
[23] C. Lageweg, S. Cotofana, and S. Vassiliadis, “Digital to Analog Conversion Performed in Single Electron Technology,” Proc. First IEEE Conf. Nanotechnology (NANO), Oct. 2001.
[24] S. Vassiliadis, S. Cotofana, and K. Bertels, “2-1 Addition and Related Arithmetic Operations with Threshold Logic,” IEEE Trans. Computers, vol. 45, no. 9, pp. 1062-1068, Sept. 1996.
[25] B. Parhami, Computer Arithmetic— Algorithms and Hardware Design, first ed. Oxford Univ. Press, 2000.

Index Terms:
SET, single electron technology, electron counting, addition, multiplication.
Citation:
Sorin Cotofana, Casper Lageweg, Stamatis Vassiliadis, "Addition Related Arithmetic Operations via Controlled Transport of Charge," IEEE Transactions on Computers, vol. 54, no. 3, pp. 243-256, March 2005, doi:10.1109/TC.2005.40
Usage of this product signifies your acceptance of the Terms of Use.