|
| This Article | ||
| ||
| Share | ||
| Bibliographic References | ||
| Add to: | ||
 Digg  Furl  Spurl  Blink  Simpy  Google  Del.icio.us  Y!MyWeb | ||
| Search | ||
| ||
| ASCII Text | x | ||
| Peter G. Sassone, D. Scott Wills, "Scaling Up the Atlas Chip-Multiprocessor," IEEE Transactions on Computers, vol. 54, no. 1, pp. 82-87, January, 2005. | |||
| BibTex | x | ||
| @article{ 10.1109/TC.2005.12, author = {Peter G. Sassone and D. Scott Wills}, title = {Scaling Up the Atlas Chip-Multiprocessor}, journal ={IEEE Transactions on Computers}, volume = {54}, number = {1}, issn = {0018-9340}, year = {2005}, pages = {82-87}, doi = {http://doi.ieeecomputersociety.org/10.1109/TC.2005.12}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, } | |||
| RefWorks Procite/RefMan/Endnote | x | ||
| TY - JOUR JO - IEEE Transactions on Computers TI - Scaling Up the Atlas Chip-Multiprocessor IS - 1 SN - 0018-9340 SP82 EP87 EPD - 82-87 A1 - Peter G. Sassone, A1 - D. Scott Wills, PY - 2005 KW - Dynamic multithreading KW - chip-multiprocessor KW - scaling. VL - 54 JA - IEEE Transactions on Computers ER - | |||
[1] H. Akkary and M. Driscoll, “A Dynamic Multithreading Processor,” Proc. 31st Int'l Symp. Microarchitecture, 1998.
[2] S. Nugent, D. Wills, and J. Meindl, “A Hierarchical Block-Based Modeling Methodology for SoC in Genesys,” Proc. IEEE Int'l ASIC/SoC Conf., 2002.
[3] E. Rotenberg, Q. Jacobson, Y. Sazeides, and J. Smith, “Trace Processors,” Proc. 30th Int'l Symp. Microarchitecture, 1997.
[4] G.S. Sohi, S. Breach, and T. Vijaykumar, “Multiscalar Processors,” Proc. 22nd Ann. Int'l Symp. Computer Architecture, 1995.
[5] S. Chappell, J. Stark, S. Kim, S. Reinhardt, and Y. Patt, “Simultaneous Subordinate Microthreading,” Proc. 26th Ann. Int'l Symp. Computer Architecture, 1999.
[6] B. Nayfeh and K. Olukotun, “A Single-Chip Multiprocessor,” Computer, vol. 30, no. 9, Sept. 1997.
[7] L. Codrescu, D. Wills, and J. Meindl, “Architecture of the Atlas Chip-Multiprocessor: Dynamically Parallelizing Irregular Applications,” IEEE Trans. Computers, vol. 50, no. 1, pp. 67-82, Jan. 2001.
[8] L. Codrescu and D. Wills, “On Dynamic Speculative Thread Partitioning and the Mem-Slicing Algorithm,” Proc. Seventh Ann. Int'l Conf. Parallel Architectures and Compilation Techniques, 1999.
[9] V. Sarkar and J. Hennessy, “Partitioning Parallel Programs for Macro-Dataflow,” Proc. 1986 ACM Conf. Lisp and Functional Programming, 1986.
[10] Z. Purser, K. Sundaramoorthy, and E. Rotenberg, “A Study of Slipstream Processors,” Proc. 33rd Int'l Symp. Microarchitecture, 2000.
[11] J. Steffan, C. Colohan, A. Zhai, and T. Mowry, “A Scalable Approach to Thread-Level Speculation,” Proc. 27th Int'l Symp. Computer Architecture, 2000.
[12] S. Wilton and N. Jouppi, “Cacti: An Enhanced Cache Access and Cycle Time Model,” IEEE J. Solid State Circuits, vol. 31, no. 5, May 1996.
[13] “Intel Microprocessor Quick Reference Guide,” http://www.intel.com/pressroom/kitsquickreffam.htm , 2003.
[14] I.T.R. for Semiconductors, “Executive Summary, 2003 Edition,” http://public.itrs.net/Files/2003ITRSExecSum2003.pdf , 2004.
[15] D. Burger and T. Austin, “The Simplescalar Tool Set, version 2.0,” Technical Report 1342, Computer Science Dept., Univ. of Wisconsin-Madison, 1997.
[16] C. Lee, M. Potkonjak, and W. Mangione-Smith, “Mediabench: A Tool for Evaluating Multimedia and Communications Systems,” Proc. 30th Int'l Symp. Microarchitecture, 1997.