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Cache Conscious Data Layout Organization for Conflict Miss Reduction in Embedded Multimedia Applications
January 2005 (vol. 54 no. 1)
pp. 76-81
Cache misses form a major bottleneck for real-time multimedia applications due to the off-chip accesses to the main memory. This results in both a major access bandwidth overhead (and related power consumption) as well as performance penalties. In this paper, we propose a new technique for organizing data in the main memory for data dominated multimedia applications so as to reduce the majority of the conflict cache misses. The focus of this paper is on the formal and heuristic algorithm we use to steer the data layout decisions and the experimental results obtained using a prototype tool. Experiments on real-life demonstrators illustrate that we are able to reduce up to 82 percent of the conflict misses for applications which are already aggressively transformed at source-level. At the same time, we also reduce the off-chip data accesses by up to 78 percent. In addition, we are able to reduce up to 20 percent more conflict misses compared to existing techniques.

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Index Terms:
RISC/CISC, VLIW architectures, VLSI systems.
Citation:
C. Kulkarni, C. Ghez, M. Miranda, F. Catthoor, H. De Man, "Cache Conscious Data Layout Organization for Conflict Miss Reduction in Embedded Multimedia Applications," IEEE Transactions on Computers, vol. 54, no. 1, pp. 76-81, Jan. 2005, doi:10.1109/TC.2005.2
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