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A Hardware Algorithm for Modular Multiplication/Division
January 2005 (vol. 54 no. 1)
pp. 12-21
A mixed radix-4/2 algorithm for modular multiplication/division suitable for VLSI implementation is proposed. The algorithm is based on Montgomery method for modular multiplication and on the extended Binary GCD algorithm for modular division. Both algorithms are modified and combined into the proposed algorithm so that almost all the hardware components are shared. The new algorithm carries out both calculations using simple operations such as shifts, additions, and subtractions. The radix-2 signed-digit representation is used to avoid carry propagation in all additions and subtractions. A modular multiplier/divider based on the algorithm performs an n{\hbox{-}}{\rm bit} modular multiplication/division in O(n) clock cycles where the length of the clock cycle is constant and independent of n. The modular multiplier/divider has a linear array structure with a bit-slice feature and can be implemented with much smaller hardware than that necessary to implement both multiplier and divider separately.

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Index Terms:
Computer arithmetic, hardware algorithm, modular multiplication, modular division, redundant representation, cryptography.
Citation:
Marcelo E. Kaihara, Naofumi Takagi, "A Hardware Algorithm for Modular Multiplication/Division," IEEE Transactions on Computers, vol. 54, no. 1, pp. 12-21, Jan. 2005, doi:10.1109/TC.2005.1
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