This Article 
   
 Share 
   
 Bibliographic References 
   
 Add to: 
 
Digg
Furl
Spurl
Blink
Simpy
Google
Del.icio.us
Y!MyWeb
 
 Search 
   
A Gaussian Noise Generator for Hardware-Based Simulations
December 2004 (vol. 53 no. 12)
pp. 1523-1534
Hardware simulation offers the potential of improving code evaluation speed by orders of magnitude over workstation or PC-based simulation. We describe a hardware-based Gaussian noise generator used as a key component in a hardware simulation system, for exploring channel code behavior at very low bit error rates (BERs) in the range of 10^{-9} to 10^{-10}. The main novelty is the design and use of nonuniform piecewise linear approximations in computing trigonometric and logarithmic functions. The parameters of the approximation are chosen carefully to enable rapid computation of coefficients from the inputs while still retaining high fidelity to the modeled functions. The output of the noise generator accurately models a true Gaussian Probability Density Function (PDF) even at very high \sigma values. Its properties are explored using: 1) several different statistical tests, including the chi-square test and the Anderson-Darling test, and 2) an application for decoding of Low-Density Parity-Check (LDPC) codes. An implementation at 133MHz on a Xilinx Virtex-II XC2V4000-6 FPGA produces 133 million samples per second, which is seven times faster than a 2.6GHz Pentium-IV PC; another implementation on a Xilinx Spartan-IIE XC2S300E-7 FPGA at 62MHz is capable of a three times speedup. The performance can be improved by exploiting parallelism: An XC2V4000-6 FPGA with nine parallel instances of the noise generator at 105MHz can run 50 times faster than a 2.6GHz Pentium-IV PC. We illustrate the deterioration of clock speed with the increase in the number of instances.

[1] J.H. Ahrens and U. Dieter, “An Alias Method for Sampling from the Normal Distribution,” Computing, vol. 42, nos. 2-3, pp. 159-170, 1989.
[2] E. Antelo, T. Lang, and J.D. Bruguera, “Very-High Radix CORDIC Vectoring with Scalings and Selection by Rounding,” Proc. IEEE Symp. Computer Arithmetic, pp. 204-213, 1999.
[3] D.R. Barr and N.L. Sezak, “A Comparison of Multivariate Normal Generators,” Comm. ACM, vol. 15, no. 12, pp. 1048-1049, 1972.
[4] A. Brace, D. Gatarek, and M. Musiela, “The Market Model of Interest Rate Dynamics,” Math. Finance, vol. 7, no. 2, pp. 127-155, 1997.
[5] A.R. Bergstrom, Econometric Theory, vol. 13, no. 467, 1997.
[6] E. Boutillon, J.L. Danger, and A. Gazel, “Design of High Speed AWGN Communication Channel Emulator,” Analog Integrated Circuits and Signal Processing, vol. 34, no. 2, pp. 133-142, 2003.
[7] G.E.P. Box and M.E. Muller, “A Note on the Generation of Random Normal Deviates,” Annals Math. and Statistics, vol. 29, pp. 610-611, 1958.
[8] J. Cao, B.W.Y. We, and J. Cheng, “High-Performance Architectures for Elementary Function Generation,” Proc. 15th IEEE Symp. Computer Arithmetic, 2001.
[9] A. Cantoni, “Optimal Curve Fitting with Piecewise Linear Functions,” IEEE Trans. Computers, vol. 20, no. 1, pp. 59-67, 1971.
[10] Celoxica Ltd., Handel-C Language Reference Manual, version 3.1, document number RM-1003-3.0, 2002.
[11] P.P. Chu and R.E. Jones, “Design Techniques of FPGA Based Random Number Generator,” Proc. Military and Aerospace Applications of Programming Devices and Techniques Conf., 1999.
[12] M. Combet, H. Van Zonneveld, and L. Verbeek, “Computation of the Base Two Logarithm of Binary Numbers,” IEEE Trans. Electronic Computers, vol. 14, no. 6, pp. 863-867, 1965.
[13] R.B. D'Agostino and M.A Stephens, Goodness-of-Fit Techniques. Marcel Dekker Inc., 1986.
[14] D. Derrien and E. Boutillon, “Quality Measurement of a Colored Gaussian Noise Generator Hardware Implementation Based on Statistical Properties,” Proc. IEEE Int'l Symp. Signal Processing and Information Technology, 2002.
[15] J.J. Eggers, J.K. Su, and B. Girod, “Robustness of a Blind Image Watermarking Scheme,” Proc. IEEE Int'l Conf. Image Processing, vol. 3, pp. 17-20, 2000.
[16] D. Das and D.W. Matula, “Faithful Bipartite Rom Reciprocal Tables,” Proc. 12th IEEE Symp. Computer Arithmetic, pp. 17-28, 1995.
[17] R.G. Gallager, “Low-Density Parity-Check Codes,” IEEE Trans. Information Theory, vol. 8, pp. 21-28, 1962.
[18] C.W. Gardiner, Handbook of Stochastic Methods. Springer-Verlag, 1990.
[19] W. Hörmann and J. Leydold, “Continuous Random Variate Generation by Fast Numerical Inversion,” ACM Trans. Modeling and Computer Simulation, vol. 13, no. 4, pp. 347-362, 2003.
[20] V.K. Jain, S.A. Wadecar, and L. Lin, “A Universal Nonlinear Component and Its Application to WSI,” IEEE Trans. Components, Hybrids, and Manufacturing Technology, vol. 16, no. 7, pp. 656-664, 1993.
[21] C. Jones, E. Vallés, M. Smith, J. Villasenor, “Approximate-Min* Constraint Node Updating for LDPC Code Decoding,” Proc. IEEE Military Comm. Conf. (MILCOM), 2003.
[22] B. Jung, H. Lenhof, P. Müller, and C. Rüb, “Langevin Dynamics Simulations of Macromolecules on Parallel Computers,” Macromolecular Theory Simululation, pp. 507-521, 1997.
[23] D.E. Knuth, “Seminumerical Algorithms” The Art of Computer Programming, volume 2, third ed., Addison-Wesley, 1997.
[24] R.E. Ladner and M.J. Fischer, “Parallel Prefix Computation,” J. ACM, vol. 27, no. 4, pp. 831-838, 1980.
[25] D. Lee, W. Luk, J. Villasenor, and P.Y.K. Cheung, “A Hardware Gaussian Noise Generator for Channel Code Evaluation,” Proc. IEEE Symp. Field-Programmable Custom Computing Machines, pp. 69-78, 2003.
[26] D. Lee, W. Luk, J. Villasenor, and P.Y.K. Cheung, “Hardware Function Evaluation Using Non-Linear Segments,” Proc. Field-Programmable Logic and Applications, pp. 796-807, 2003.
[27] D. Lee, W. Luk, J. Villasenor, and P.Y.K. Cheung, “Hierarchical Segmentation Schemes for Function Evaluation,” Proc. IEEE Int'l Conf. on Field-Programmable Technology, pp. 92-99, 2003.
[28] D. Lee, W. Luk, C. Wang, C. Jones, M. Smith, and J. Villasenor, “A Flexible Hardware Encoder for Low-Density Parity-Check Codes,” Proc. IEEE Symp. Field-Programmable Custom Computing Machines, 2004.
[29] J.L. Leva, “A Fast Normal Random Number Generator,” ACM Trans. Math. Software, vol. 18, no. 4, pp. 449-453, 1992.
[30] B. Levine, R.R. Taylor, and H. Schmit, “Implementation of Near Shannon Limit Error-Correcting Codes Using Reconfigurable Hardware,” Proc. IEEE Symp. Field-Programmable Custom Computing Machines, pp. 217-226, 2000.
[31] J. Leydold, “Automatic Sampling with the Ratio-of-Uniforms Method,” ACM Trans. Math. Software, vol. 26, no. 1, pp. 78-98, 2000.
[32] D.J.C. MacKay, “Good Error-Correcting Codes Based on Very Sparse Matrices,” IEEE Trans. Information Theory, Mar. 1999.
[33] G. Marsaglia, M.D. MacLaren, and T.A. Bray, “A Fast Procedure for Generating Normal Random Variables,” Comm. ACM, vol. 7, no. 1, pp. 4-10, 1964.
[34] G. Marsaglia, Diehard: A Battery of Tests of Randomness, http://stat.fsu.edu/~geodiehard.html, 1997.
[35] G. Marsaglia and W.W. Tsang, “The Monty Python Method for Generating Random Variables,” ACM Trans. Math. Software, vol. 24, no. 3, pp. 341-350, 1998.
[36] G. Marsaglia and W.W. Tsang, “The Ziggurat Method for Generating Random Variables,” J. Statistical Software, vol. 5, no. 8, pp. 1-7, 2000.
[37] O. Mencer and W. Luk, “Parameterized High Throughput Function Evaluation for FPGAs,” J. VLSI Signal Processing Systems, vol. 36, no. 1, pp. 17-25, 2004.
[38] A. Miller and M. Gulotta, “PN Generators Using the SRL Macro,” Xilinx Application Note XAPP211, v1. 1, 2001.
[39] M.E. Muller, “A Comparison of Methods for Generating Normal Deviates on Digital Computers,” J. ACM, vol. 6, no. 3, pp. 376-383, 1959.
[40] J.N. Mitchell Jr., “Computer Multiplication and Division Using Binary Logarithms,” IRE Trans. Electronic Computers, vol. 11, pp. 512-517, 1962.
[41] J.M. Muller, Elementary Functions: Algorithms and Implementation. Birkhauser Verlag AG, 1997.
[42] R.H. Morelos-Zaragoza, The Art of Error Correcting Coding. John Wiley & Sons, 2002.
[43] Nallatech, BenONE User Guide, http:/www.nallatech.com, 2002.
[44] A.S. Noetzel, “An Interpolating Memory Unit for Function Evaluation: Analysis and Design,” IEEE Trans. Computers, vol. 38, pp. 377-384, 1989.
[45] W.H. Payne, “Normal Random Numbers: Using Machine Analysis to Choose the Best Algorithm,” ACM Trans. Math. Software, vol. 3, no. 4, pp. 346-358, 1977.
[46] J.A Piñeiro, J.D. Bruguera, and J.M. Muller, “Faithful Powering Computation Using Table Look-Up and a Fused Accumulation Tree,” Proc. 15th IEEE Symp. Computer Arithmetic, 2001.
[47] T. Richardson and R. Urbanke, “Efficient Encoding of Low-Density Parity-Check Codes,” IEEE Trans. Information Theory, vol. 47, pp. 638-656, 2001.
[48] B.D. Ripley, Stochastic Simulation. Wiley, 1987.
[49] C. Rose, J. Economic Dynamics and Control, vol. 19, no. 1391, 1997.
[50] M.F. Schollmeyer and W.H. Tranter, “Noise Generators for the Simulation Of Digital Communication Systems,” Proc. 24th Ann. Simulation Symp., pp. 264-275, 1991.
[51] J. Vedral and J. Holub, “Oscilloscope Testing by Means of Stochastic Signal,” Measurement Science Rev., vol. 1, no. 1, 2001.
[52] Xilinx Inc., Virtex-II User Guide v1.5, 2002.
[53] J.E. Volder, “The CORDIC Trigonometric Computing Technique,” IEEE Trans. Electronic Computers, vol. 8, no. 3, pp. 330-334, 1959.
[54] N. Wax, Noise and Stochastic Processes. Donver Publications, 1954.
[55] “Additive White Gaussian Noise (AWGN) Core v1.0,” Xilinx Product Specification, 2002.
[56] K.W. Yip and T.S. Ng, “A Simulation Model for Nakagami-$m$ Fading Channels, $m<1$ ,” IEEE Trans. Comm., vol. 48, no. 2, pp. 214-221, 2000.

Index Terms:
Algorithms implemented in hardware, error-checking, gate arrays, simulation.
Citation:
Dong-U Lee, Wayne Luk, John D. Villasenor, Peter Y.K. Cheung, "A Gaussian Noise Generator for Hardware-Based Simulations," IEEE Transactions on Computers, vol. 53, no. 12, pp. 1523-1534, Dec. 2004, doi:10.1109/TC.2004.106
Usage of this product signifies your acceptance of the Terms of Use.