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Performance and Area Modeling of Complete FPGA Designs in the Presence of Loop Transformations
November 2004 (vol. 53 no. 11)
pp. 1420-1435
Selecting which program transformations to apply when mapping computations to FPGA-based computing architectures can lead to prohibitively long design space exploration cycles. An alternative is to develop fast, yet accurate, performance and area models to quickly understand the impact and interaction of the transformations. In this paper, we present a combined analytical performance and area modeling approach for complete FPGA designs in the presence of loop transformations. Our approach takes into account the impact of input/output memory bandwidth and memory interface resources, often the limiting factor in the effective implementation of computations. Our preliminary results reveal that our modeling is very accurate, being therefore amenable to be used in a compiler tool to quickly explore very large design spaces.

[1] J. Park and P. Diniz, Synthesis of Memory Access Controller for Streamed Data Applications for FPGA-Based Computing Engines Proc. 14th Int'l Symp. System Synthesis (ISSS 2001), 2001.
[2] M. Wolf and M. Lam, “A Loop Transformation Theory and an Algorithm to Maximize Parallelism,” IEEE Trans. Parallel and Distributed Systems, vol. 2, no. 4, Oct. 1991.
[3] B. So and M. Hall, Increasing the Applicability of Scalar Replacement Proc. Int'l Conf. Compiler Construction (CC '04), pp. 185-201, 2004.
[4] U. Banerjee, R. Eigenman, A. Nicolau, and D. Padua, Automatic Program Parallelization. IEEE, 1993.
[5] M. Kandemir and A. Choudhary, Compiler-Directed Scratch Pad Memory Hierarchy Design and Management Proc. 2002 ACM/IEEE Design Automation Conf. (DAC '02), 2002.
[6] Xilinx, Virtex 2.5v FPGA Product Specification. ds003(v2.4) 2000.
[7] Annapolis MicroSystems, Wildstar Reference Manual rev. 4.0 1999.
[8] D. Kulkarni, W. Najjar, R. Rinker, and F. Kurdah, Fast Area Estimation to Support Compiler Optimizations in FPGA-Based Reconfigurable Systems Proc. 2002 Symp. Field-Programmable Custom Computing Machines (FCCM '02), 2002.
[9] A. Nayak, M. Haldar, A. Choudhary, and P. Banerjee, Accurate Area and Delay Estimators for FPGAs Proc. Design Automation and Test in Europe Conf. and Exhibition (DATE '02), 2002.
[10] M. Kaul, R. Vemuri, S. Givindarajan, and I.E. Ouaiss, An Automated Temporal Partitioning and Loop Fission Approach to FPGA Based Reconfigurable Synthesis of DSP Applications Proc. IEEE/ACM Design Automation Conf. (DAC '99), 1999.
[11] J. Cardoso, Loop Dissevering: A Technique for Temporally Partitioning Loops in Dynamically Reconfigurable Computing Platforms Proc. 10th Reconfigurable Architectures Workshop (RAW 2003), 2002.
[12] B. So, M. Hall, and P. Diniz, A Compiler Approach to Fast Hardware Design Space Exploration for FPGA Systems Proc. 2002 ACM Conf. Programming Language Design and Implementation (PLDI '02), pp. 165-176, 2002.
[13] S. Derrien and S. Rajoupadyhe, Loop Tiling for Reconfigurable Accelerators Proc. 11th Int'l Symp. Field-Programmable Logic (FPL 2001), 2001.
[14] J. Liao, W.F. Wong, and T. Mitra, A Model for the Hardware Realization of Loops Proc. 2003 Int'l Symp. Field Programmable Logic and Applications (FPL '03), pp. 334-344, 2003.
[15] V. Kathail, S. Aditya, R. Schreiber, B. Rau, D. Cronquist, and M. Sivaraman, PICO: Automatically Designing Custom Computers Computer, 2002.
[16] A. Bakshi, V. Prasanna, and A. Ledeczi, MILAN: A Model Based Integrated Simulation Framework for Design of Embedded Systems Proc. 2001 Workshop Languages, Compilers, and Tools for Embedded Systems (LCTES 2001), 2001.
[17] A. Halambi et al., "EXPRESSION: A Language for Architecture Exploration through Compiler/Simulator Retargetability," Proc. Design Automation and Test in Europe (DATE 99), IEEE CS Press, 1999, pp. 485-490.

Index Terms:
Performance analysis and modeling, loop transformations and high-level synthesis, configurable computing, Field-Programmable-Gate-Arrays (FPGAs).
Joonseok Park, Pedro C. Diniz, K.R. Shesha Shayee, "Performance and Area Modeling of Complete FPGA Designs in the Presence of Loop Transformations," IEEE Transactions on Computers, vol. 53, no. 11, pp. 1420-1435, Nov. 2004, doi:10.1109/TC.2004.101
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