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Performance and Area Modeling of Complete FPGA Designs in the Presence of Loop Transformations
November 2004 (vol. 53 no. 11)
pp. 1420-1435
Selecting which program transformations to apply when mapping computations to FPGA-based computing architectures can lead to prohibitively long design space exploration cycles. An alternative is to develop fast, yet accurate, performance and area models to quickly understand the impact and interaction of the transformations. In this paper, we present a combined analytical performance and area modeling approach for complete FPGA designs in the presence of loop transformations. Our approach takes into account the impact of input/output memory bandwidth and memory interface resources, often the limiting factor in the effective implementation of computations. Our preliminary results reveal that our modeling is very accurate, being therefore amenable to be used in a compiler tool to quickly explore very large design spaces.

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Index Terms:
Performance analysis and modeling, loop transformations and high-level synthesis, configurable computing, Field-Programmable-Gate-Arrays (FPGAs).
Citation:
Joonseok Park, Pedro C. Diniz, K.R. Shesha Shayee, "Performance and Area Modeling of Complete FPGA Designs in the Presence of Loop Transformations," IEEE Transactions on Computers, vol. 53, no. 11, pp. 1420-1435, Nov. 2004, doi:10.1109/TC.2004.101
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