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An Asynchronous Dataflow FPGA Architecture
November 2004 (vol. 53 no. 11)
pp. 1376-1392
Web Extra: View supplemental material
We discuss the design of a high-performance field programmable gate array (FPGA) architecture that efficiently prototypes asynchronous (clockless) logic. In this FPGA architecture, low-level application logic is described using asynchronous dataflow functions that obey a token-based compute model. We implement these dataflow functions using finely pipelined asynchronous circuits that achieve high computation rates. This asynchronous dataflow FPGA architecture maintains most of the performance benefits of a custom asynchronous design, while also providing postfabrication logic reconfigurability. We report results for two asynchronous dataflow FPGA designs that operate at up to 400 MHz in a typical TSMC 0.25\mu m CMOS process.

[1] V. Betz and J. Rose, VPR: A New Packing, Placement, and Routing Tool for FPGA Research Proc. Int'l Workshop Field Programmable Logic and Applications, 1997.
[2] U.V. Cummings, A.M. Lines, and A.J. Martin, An Asynchronous Pipeline Lattice-Structure Filter Proc. Int'l Symp. Asynchronous Circuits and Systems, 1994.
[3] J.B. Dennis, The Evolution of 'Static' Data-Flow Architecture Advanced Topics in Data-Flow Computing, J.-L. Gaudiot and L. Bic, eds., Prentice Hall, 1991.
[4] G. Goslin, A Guide to Using {FPGAs for Application-Specific Digital Signal Processing Performance Xilinx Application Notes, 1995.
[5] S. Hauck, S. Burns, G. Borriello, and C. Ebeling, An FPGA for Implementing Asynchronous Circuits IEEE Design and Test of Computers, vol. 11, no. 3, pp. 60-69, 1994.
[6] B. Von Herzen, Signal Processing at 250 Mhz Using High-Performance FPGAs Proc. Int'l Symp. Field Programmable Gate Arrays, 1997.
[7] Q.T. Ho, J.-B Rigaud, L. Fesquet, M. Renaudin, and R. Rolland, Implementing Asynchronous Circuits on LUT Based FPGAs Proc. Int'l Conf. Field Programmable Logic and Applications, 2002.
[8] D.L. How, A Self Clocked FPGA for General Purpose Logic Emulation Proc. IEEE Custom Integrated Circuits Conf., 1996.
[9] R. Konishi, H. Ito, H. Nakada, A. Nagoya, K. Oguri, N. Imlig, T. Shiozawa, M. Inamori, and K. Nagami, PCA-1: A Fully Asynchronous Self-Reconfigurable LSI Proc. Int'l Symp. Asynchronous Circuits and Systems, 2001.
[10] S.Y. Kung, VLSI Array Processors. Prentice Hall, 1988.
[11] A. Lines, Pipelined Asynchronous Circuits master's thesis, California Inst. of Tech nology, 1995.
[12] K. Maheswaran, Implementing Self-Timed Circuits in Field Programmable Gate Arrays master's thesis, Univ. of California Davis, 1995.
[13] R. Manohar, A Case for Asynchronous Computer Architecture Proc. ISCA Workshop Complexity-Effective Design, 2000.
[14] R. Manohar and A.J. Martin, Slack Elasticity in Concurrent Computing Proc. Int'l Conf. Math. of Program Construction, 1998.
[15] A.J. Martin, The Limitations to Delay-Insensitivity in Asynchronous Circuits Proc. Conf. Advanced Research in VLSI, 1990.
[16] A. Martin, A. Lines, R. Manohar, M. Nystrm, P. Penzes, R. Southworth, U. Cummings, and T. Lee, The Design of an Asynchronous MIPS R3000 Microprocessor Proc. 17th Conf. Advanced Research in VLSI, Sept. 1997.
[17] R. Payne, Asynchronous FPGA Architectures IEE Computers and Digital Techniques, vol. 143, no. 5, 1996.
[18] A. Singh, A. Mukherjee, and M. Marek-Sadowska, Interconnect Pipelining in a Throughput Intensive FPGA Architecture Proc. Int'l Symp. Field Programmable Gate Arrays, 2001.
[19] J. Teifel, D. Fang, D. Biermann, C. Kelly, and R. Manohar, Energy-Efficient Pipelines Proc. Int'l Symp. Asynchronous Circuits and Systems, Apr. 2002.
[20] J. Teifel and R. Manohar, Programmable Asynchronous Pipeline Arrays Proc. Int'l Conf. Field Programmable Logic and Applications, Sept. 2003.
[21] J. Teifel and R. Manohar, Highly Pipelined Asynchronous FPGAs Proc. Int'l Symp. Field Programmable Gate Arrays, Feb. 2004.
[22] J. Teifel and R. Manohar, Static Tokens: Using Dataflow to Automate Concurrent Pipeline Synthesis Proc. Int'l Symp.n Asynchronous Circuits and Systems, Apr. 2004.
[23] C. Traver, R.B. Reese, and M.A. Thornton, Cell Designs for Self-Timed FPGAs Proc. ASIC/SOC Conf., 2001.
[24] W. Tsu, K. Macy, A. Joshi, R. Huang, N. Walker, T. Tung, O. Rowhani, V. George, J. Wawrzynek, and A. DeHon, HSRA: High-Speed, Hierarchical Synchronous Reconfigurable Array Proc. Int'l Symp. Field Programmable Gate Arrays, 1999.
[25] N. Weaver, J. Hauser, and J. Wawrzynek, The SFRA: A Corner-Turn FPGA Architecture Proc. Int'l Symp. Field Programmable Gate Arrays, Feb. 2004.
[26] T.E. Williams, Self-Timed Rings and Their Application to Division PhD thesis, Stanford Univ., 1991.
[27] Xilinx, Virtex 2.5V Field Programmable Gate Arrays Xilinx Data Sheet, 2002.

Index Terms:
Asynchronous/synchronous operation, dataflow architectures, gate arrays, reconfigurable hardware.
Citation:
John Teifel, Rajit Manohar, "An Asynchronous Dataflow FPGA Architecture," IEEE Transactions on Computers, vol. 53, no. 11, pp. 1376-1392, Nov. 2004, doi:10.1109/TC.2004.88
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