Issue No.10 - October (2004 vol.53)
V?ctor Vi?als , IEEE
Jos? Gonz?lez , IEEE Computer Society
Antonio Gonz?lez , IEEE Computer Society
Mateo Valero , IEEE
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/TC.2004.79
The Register File is one of the critical components of current processors in terms of access time and power consumption. Among other things, the potential to exploit instruction-level parallelism is closely related to the size and number of ports of the register file. In conventional register renaming schemes, both register allocation and releasing are conservatively done, the former at the rename stage, before registers are loaded with values, and the latter at the commit stage of the instruction redefining the same register, once registers are not used anymore. In this paper, we introduce VP-LAER, a renaming scheme that allocates registers later and releases them earlier than conventional schemes. Specifically, physical registers are allocated at the end of the execution stage and released as soon as the processor realizes that there will be no further use of them. VP-LAER enhances register utilization, that is, the fraction of allocated registers having a value to be read in the future. Detailed cycle-level simulations show either a significant speedup for a given register file size or a reduction in the register file size for a given performance level, especially for floating-point codes, where the register file pressure is usually high.
Register renaming, out-of-order processors, register file optimization, physical register allocation and releasing, precise exceptions.
Teresa Monreal, V?ctor Vi?als, Jos? Gonz?lez, Antonio Gonz?lez, Mateo Valero, "Late Allocation and Early Release of Physical Registers", IEEE Transactions on Computers, vol.53, no. 10, pp. 1244-1259, October 2004, doi:10.1109/TC.2004.79