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Fast Parallel-Prefix Modulo 2^n+1 Adders
September 2004 (vol. 53 no. 9)
pp. 1211-1216
Modulo 2^n+1 adders find great applicability in several applications including RNS implementations and cryptography. In this paper, we present two novel architectures for designing modulo 2^n+1 adders, based on parallel-prefix carry computation units. The first architecture utilizes a fast carry increment stage, whereas the second is a totally parallel-prefix solution. CMOS implementations reveal the superiority of the resulting adders against previously reported solutions in terms of implementation area and execution latency.

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Index Terms:
Binary adders, modulo 2^n+1 arithmetic, parallel-prefix adders, RNS.
Costas Efstathiou, Haridimos T. Vergos, Dimitris Nikolos, "Fast Parallel-Prefix Modulo 2^n+1 Adders," IEEE Transactions on Computers, vol. 53, no. 9, pp. 1211-1216, Sept. 2004, doi:10.1109/TC.2004.60
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