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Fast Parallel-Prefix Modulo 2^n+1 Adders
September 2004 (vol. 53 no. 9)
pp. 1211-1216
Modulo 2^n+1 adders find great applicability in several applications including RNS implementations and cryptography. In this paper, we present two novel architectures for designing modulo 2^n+1 adders, based on parallel-prefix carry computation units. The first architecture utilizes a fast carry increment stage, whereas the second is a totally parallel-prefix solution. CMOS implementations reveal the superiority of the resulting adders against previously reported solutions in terms of implementation area and execution latency.

[1] N. Szabo and R. Tanaka, Residue Arithmetic and Its Aplications to Computer Technology. McGraw-Hill, 1967.
[2] M.A. Soderstrand et al., Residue Number System Arithmetic: Modern Applications in Digital Signal Processing. IEEE Press, 1986.
[3] F. Taylor, A Single Modulus ALU for Signal Processing IEEE Trans. Acoustics, Speech, Signal Processing, vol. 33, pp. 1302-1315, 1985.
[4] E.D. Claudio et al., Fast Combinatorial RNS Processors for DSP Applications IEEE Trans. Computers, vol. 44, pp. 624-633, 1995.
[5] J. Ramirez et al., RNS-Enabled Digital Signal Processor Design Electronics Letters, vol. 38, no. 6, pp. 266-268, 2002.
[6] High Performance, Reduced Complexity Programmable RNS-FPL Merged FIR Filters Electronics Letters, vol. 38, no. 4, pp. 199-200, 2002.
[7] P.G. Fernandez et al., A RNS-Based Matrix-Vector-Multiply FCT Architecture for DCT Computation Proc. 43rd IEEE Midwest Symp. Circuits and Systems, pp. 350-353, 2000.
[8] J. Ramirez et al., Fast RNS FPL-Based Communications Receiver Design and Implementation Proc. 12th Int'l Conf. Field Programmable Logic, pp. 472-481, 2002.
[9] T. Keller et al., Adaptive Redundant Residue Number System Coded Multicarrier Modulation IEEE J. Selected Areas in Comm., vol. C-18, no. 11, pp. 2292-2301, 2000.
[10] V. Paliouras and T. Stouraitis, Novel High-Radix Residue Number System Multipliers and Adders Proc. IEEE Int'l Symp. Circuits and Systems, pp. 451-454, 1999.
[11] R. Zimmermann et al., A 177 Mb/s VLSI Implementation of the International Data Encryption Algorithm IEEE} J. Solid-State Circuits, vol. 29, no. 3, pp. 303-307, 1994.
[12] A. Curiger, VLSI Architectures for Computations in Finite Rings and Fields PhD dissertation, Swiss Federal Inst. of Tech nology, 1993.
[13] H. Nozaki et al., Implementation of RSA Algorithm Based on RNS Montgomery Multiplication Proc. Third Int'l Workshop Cryptographic Hardware and Embedded Systems, pp. 364-376, 2001.
[14] Y. Ma, A Simplified Architecture for Modulo$(2^n+1)$Multiplication IEEE Trans. Computers, vol. 47, no. 3, pp. 333-337, Mar. 1998.
[15] L.M. Leibowitz, A Simplified Binary Arithmetic for the Fermat Number Transform IEEE Trans. Acoustics, Speech, Signal Processing, vol. 24, pp. 356-359, 1976.
[16] R. Zimmermann, Binary Adder Architectures for Cell-Based VLSI and Their Synthesis PhD dissertation, Swiss Federal Inst. of Tech nology, 1997.
[17] R. Zimmerman, Efficient VLSI Implementation of Modulo$(2^n\pm 1)$Addition and Multiplication Proc. 14th IEEE Symp. Computer Arithmetic, pp. 158-167, Apr. 1999.
[18] C. Efstathiou et al., On the Design of Modulo$2^{n}\pm1$Adders Proc. Eighth IEEE Int'l Conf. Electronics, Circuits&Systems, pp. 517-520, 2001.
[19] H.T. Vergos et al., Diminished-One Modulo$2^n+1$Adder Design IEEE Trans. Computers, vol. 51, pp. 1389-1399, 2002.
[20] M. Bayoumi and G. Jullien, A VLSI Implementation of Residue Adders IEEE Trans. Circuits Systems, vol. 34, pp. 284-288, 1987.
[21] M. Dugdale, VLSI Implementation of Residue Adders Based on Binary Adders IEEE Trans. Circuits Systems II, vol. 39, pp. 325-329, 1992.
[22] A.A. Hiasat, High-Speed and Reduced Area Modular Adder Structures for RNS IEEE Trans. Computers, pp. 84-89, 2002.
[23] J.A. Abraham and D.D. Gajski, Easily Testable High-Speed Realization of Register-Transfer-Level Operations Proc. 10th Fault Tolerant Computing Symp., pp. 339-344, 1980.
[24] L. Kalampoukas et al., High-Speed Parallel-Prefix Modulo$2^n-1$Adders IEEE Trans. Computers, vol. 49, no. 7, pp. 673-680, July 2000.
[25] R.E. Ladner and M.J. Fischer, Parallel Prefix Computation J. ACM, vol. 27, no. 4, pp. 831-838, 1980.
[26] R.P. Brent and H.T. Kung, A Regular Layout for Parallel Adders IEEE Trans. Computers, vol. 31, no. 3, pp. 260-264, 1982.
[27] P.M. Kogge and H.S. Stone, A Parallel Algorithm for the Efficient Solution of a General Class of Recurrence Equations IEEE Trans. Computers, vol. 22, pp. 786-792, 1973.
[28] S Knowles, “A Family of Adders,” Proc. 14th IEEE Symp. Computer Arithmetic, pp. 30-34, July 1999.
[29] A. Tyagi, A Reduced-Area Scheme for Carry-Select Adders IEEE Trans. Computers, vol. 42, no. 10, Oct. 1993.

Index Terms:
Binary adders, modulo 2^n+1 arithmetic, parallel-prefix adders, RNS.
Citation:
Costas Efstathiou, Haridimos T. Vergos, Dimitris Nikolos, "Fast Parallel-Prefix Modulo 2^n+1 Adders," IEEE Transactions on Computers, vol. 53, no. 9, pp. 1211-1216, Sept. 2004, doi:10.1109/TC.2004.60
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