This Article 
 Bibliographic References 
 Add to: 
Universal Delay-Insensitive Circuits with Bidirectional and Buffering Lines
August 2004 (vol. 53 no. 8)
pp. 1034-1046

Abstract—Delay-Insensitive (DI) circuits are a class of asynchronous circuits whose correctness of operation is robust to arbitrary delays in modules or interconnection lines. Keller clarified the precise operating conditions of the class of DI-circuits and presented a universal set of primitive modules from which any circuit in the class is realizable. Later, Patra and Fussell presented an alternative universal set of primitive modules and claimed that there is no universal set of primitives satisfying Keller's conditions in which the largest number of input and output lines of each primitive module is less than five. In this paper, we present new types of primitive modules, each having at most three input and output-lines and show they form a universal set of primitives. We achieve this reduction in complexity by allowing the input and output-lines of modules to be bidirectional and to be able to buffer signals. The use of buffers in interconnection lines allows higher throughput of signals and results in circuits requiring less feedback lines, thus improving the efficiency of DI-circuits. The proposed class of DI-circuits is especially useful for implementations on cellular automata—an architecture that promises efficient implementations and manufacturing in nanotechnology due to its regular structure.

[1] S. Adachi, F. Peper, and J. Lee, Computation by Asynchronously Updating Cellular Automata J. Statistical Physics, vol. 114, nos. 1-2, pp. 261-289, 2004.
[2] P. Beckett and A. Jennings, Towards Nanocomputer Architecture Proc. Seventh Asia-Pacific Computer Systems Architecture Conf. ACSAC 2002 (Conf. Research and Practice in Information Technology), F. Lain and J. Morris, eds., vol. 6, 2002.
[3] K. van Berkel, Handshake Circuits: An Asynchronous Architecture for VLSI Programming. Cambridge Univ. Press, 1993.
[4] K. van Berkel and A. Bink, Single-Track Handshake Signaling with Application to Micropipelines and Handshake Circuits Proc. Second Int'l Symp. Advanced Research in Asynchronous Circuits and Systems, pp. 122-133, 1996.
[5] M. Biafore, Cellular Automata for Nanometer-Scale Computation Physica D, vol. 70, pp. 415-433, 1995.
[6] J.A. Brzozowski and J.C. Ebergen, On the Delay-Sensitivity of Gate Networks IEEE Trans. Computers, vol. 41. no. 11, pp. 1349-1360, Nov. 1992.
[7] R.P. Cowburn and M.E. Welland, Room Temperature Magnetic Quantum Cellular Automata Science, vol. 287, pp. 1466-1468, 2000.
[8] A. Davis and S.M. Nowick, An Introduction to Asynchronous Circuits Design Technical Report UUCS-97-013, Computer Science Dept., Univ. of Utah, , 1997.
[9] M.E. Dean, T.E. Williams, and D.L. Dill, Efficient Self-Timing with Level-Encoded 2-Phase Dual-Rail (LEDR) Advanced Research in VLSI, pp. 55-70, 1991.
[10] L.J.K. Durbeck and N.J. Macias, The Cell Matrix: An Architecture for Nanocomputing Nanotechnology, vol. 12, pp. 217-230, 2001.
[11] J.C. Ebergen, Translating Programs into Delay-Insensitive Circuits CWI Tract, vol. 56, Centre for Math.and Computer Science, 1989.
[12] J.C. Ebergen, A Formal Approach to Designing Delay-Insensitive Circuits Distributed Computing, vol. 5, pp. 107-119, 1991.
[13] J. Ebergen, Squaring the FIFO in GasP Proc. Seventh Int'l Symp. Advanced Research in Asynchronous Circuits and Systems, pp. 194-205, 2001.
[14] E.B. Eichelberger, Hazard Detection in Combinational and Sequential Switching Circuits IBM J. Research and Development, Mar. 1965.
[15] S. Hauck, Asynchronous Design Methodologies: An Overview Proc. IEEE, vol. 83, no. 1, pp. 69-93, 1995.
[16] A.J. Heinrich, C.P. Lutz, J.A. Gupta, and D.M. Eigler, Molecule Cascades Science, vol. 298, pp. 1381-1387, 2002.
[17] D.R. Hopcroft and J.D. Ullman, Introduction to Automata Theory, Languages, and Computation. Reading, Mass.: Addision-Wesley, 1979.
[18] C. Joachim, J.K. Gimzewski, and A. Aviram, Electronics Using Hybrid-Molecular and Mono-Molecular Devices Nature, vol. 408, pp. 541-548, 2000.
[19] Y. Kameda, S.V. Polonsky, M. Maezawa, and T. Nanya, Self-Timed Parallel Adders Based on DI RSFQ Primitives IEEE Trans. Applied Superconductivity, vol. 9, no. 2, pp. 4040-4045, 1999.
[20] R.M. Keller, Towards a Theory of Universal Speed-Independent Modules IEEE Trans. Computers, vol. 23, no. 1, pp. 21-33, Jan. 1974.
[21] J. Lee, S. Adachi, F. Peper, and K. Morita, Embedding Universal Delay-Insensitive Circuits in Asynchronous Cellular Spaces Fundamenta Informaticae, 2004.
[22] J. Lee, F. Peper, S. Adachi, and S. Mashiko, On Reversible Computation in Asynchronous Systems submitted for publication.
[23] C.S. Lent and P.D. Tougaw, A Device Architecture for Computing with Quantum Dots Proc. IEEE, vol. 85, pp. 541-557, 1997.
[24] N.A. Lynch, Distributed Algorithms. Morgan Kaufmann, 1996.
[25] A.J. Martin, The Limitations to Delay-Insensitivity in Asynchronous Circuits Proc. Sixth MIT Conf. Advanced Research in VLSI, pp. 263-278, Cambridge, Mass.: MIT Press, 1990.
[26] G.H. Mealy, A Method for Synthesizing Sequential Circuits Bell System Technical J., vol. 34, no. 5, pp. 1045-1079, 1955.
[27] C.J. Myers, Asynchronous Circuit Design. New York: Wiley, 2001.
[28] K. Morita, A Simple Universal Logic Element and Cellular Automata for Reversible Computing Lecture Notes in Computer Science, vol. 2055, pp. 102-113, 2001.
[29] K. Nakamura, Asynchronous Cellular Automata and Their Computational Ability Systems, Computers, Controls, vol. 5, no. 5, pp. 58-66, 1974.
[30] J. von Neumann, Theory of Self-Reproducing Automata, A.W. Burks, ed. Univ. of Illinois Press, 1966.
[31] S.M. Ornstein, M.J. Stucki, and W.A. Clark, A Functional Description of Macromodules AFIPS Conf. Proc.: 1967 Spring Joint Computer Conf., vol. 30, pp. 337-355, 1967.
[32] P. Patra and D.S. Fussell, Building-Blocks for Designing DI Circuits Technical Report tr93-23, Dept. of Computer Sciences, Univ. of Texas at Austin, 1993.
[33] P. Patra and D.S. Fussell, Efficient Building Blocks for Delay Insensitive Circuits Proc. Int'l Symp. Advanced Research in Asynchronous Circuits and Systems, pp. 196-205, 1994.
[34] P. Patra, Approaches to Design of Circuits for Low-Power Computation PhD thesis, Univ. of Texas at Austin, 1995.
[35] P. Patra and D.S. Fussell, Conservative Delay-Insensitive Circuits Proc. Workshop Physics and Computation (PhysComp '96), 1996.
[36] P. Patra, S. Polonsky, and D.S. Fussell, Delay-Insensitive Logic for RSFQ Superconductor Technology Proc. Third Int'l Symp. Advanced Research in Asynchronous Circuits and Systems, pp. 42-53, 1997.
[37] F. Peper, J. Lee, S. Adachi, and S. Mashiko, Laying Out Circuits on Asynchronous Cellular Arrays: A Step towards Feasible Nanocomputers? Nanotechnology, vol. 14, no. 4, pp. 469-485, 2003.
[38] C.A. Petri, Communication with Automata PhD thesis, Univ. of Bonn, 1962.
[39] W. Porod, Nanoelectronic Circuit Architectures Handbook of Nanoscience, Eng., and Technology, W.A. Goddard III, D.W. Brenner, S.E. Lyshevski, and G.J. Lafrate, chapter 5, Boca Raton, Fla.: Chemical Rubber Company Press, 2002.
[40] L. Priese, Automata and Concurrency Theoretical Computer Science, vol. 25, pp. 221-265, 1983.

Index Terms:
Asynchronous systems, delay-insensitive circuits, module, universality, bidirectional buffering lines.
Jia Lee, Ferdinand Peper, Susumu Adachi, Kenichi Morita, "Universal Delay-Insensitive Circuits with Bidirectional and Buffering Lines," IEEE Transactions on Computers, vol. 53, no. 8, pp. 1034-1046, Aug. 2004, doi:10.1109/TC.2004.51
Usage of this product signifies your acceptance of the Terms of Use.