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Jia Lee, Ferdinand Peper, Susumu Adachi, Kenichi Morita, "Universal DelayInsensitive Circuits with Bidirectional and Buffering Lines," IEEE Transactions on Computers, vol. 53, no. 8, pp. 10341046, August, 2004.  
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@article{ 10.1109/TC.2004.51, author = {Jia Lee and Ferdinand Peper and Susumu Adachi and Kenichi Morita}, title = {Universal DelayInsensitive Circuits with Bidirectional and Buffering Lines}, journal ={IEEE Transactions on Computers}, volume = {53}, number = {8}, issn = {00189340}, year = {2004}, pages = {10341046}, doi = {http://doi.ieeecomputersociety.org/10.1109/TC.2004.51}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }  
RefWorks Procite/RefMan/Endnote  x  
TY  JOUR JO  IEEE Transactions on Computers TI  Universal DelayInsensitive Circuits with Bidirectional and Buffering Lines IS  8 SN  00189340 SP1034 EP1046 EPD  10341046 A1  Jia Lee, A1  Ferdinand Peper, A1  Susumu Adachi, A1  Kenichi Morita, PY  2004 KW  Asynchronous systems KW  delayinsensitive circuits KW  module KW  universality KW  bidirectional buffering lines. VL  53 JA  IEEE Transactions on Computers ER   
Abstract—DelayInsensitive (DI) circuits are a class of asynchronous circuits whose correctness of operation is robust to arbitrary delays in modules or interconnection lines. Keller clarified the precise operating conditions of the class of DIcircuits and presented a universal set of primitive modules from which any circuit in the class is realizable. Later, Patra and Fussell presented an alternative universal set of primitive modules and claimed that there is no universal set of primitives satisfying Keller's conditions in which the largest number of input and output lines of each primitive module is less than five. In this paper, we present new types of primitive modules, each having at most three input and outputlines and show they form a universal set of primitives. We achieve this reduction in complexity by allowing the input and outputlines of modules to be bidirectional and to be able to buffer signals. The use of buffers in interconnection lines allows higher throughput of signals and results in circuits requiring less feedback lines, thus improving the efficiency of DIcircuits. The proposed class of DIcircuits is especially useful for implementations on cellular automata—an architecture that promises efficient implementations and manufacturing in nanotechnology due to its regular structure.
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