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Tom? Lang, Javier D. Bruguera, "FloatingPoint MultiplyAddFused with Reduced Latency," IEEE Transactions on Computers, vol. 53, no. 8, pp. 9881003, August, 2004.  
BibTex  x  
@article{ 10.1109/TC.2004.44, author = {Tom? Lang and Javier D. Bruguera}, title = {FloatingPoint MultiplyAddFused with Reduced Latency}, journal ={IEEE Transactions on Computers}, volume = {53}, number = {8}, issn = {00189340}, year = {2004}, pages = {9881003}, doi = {http://doi.ieeecomputersociety.org/10.1109/TC.2004.44}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }  
RefWorks Procite/RefMan/Endnote  x  
TY  JOUR JO  IEEE Transactions on Computers TI  FloatingPoint MultiplyAddFused with Reduced Latency IS  8 SN  00189340 SP988 EP1003 EPD  9881003 A1  Tom? Lang, A1  Javier D. Bruguera, PY  2004 KW  Computer arithmetic KW  floatingpoint functional units KW  multiplyaddfused (MAF) operation KW  VLSI design. VL  53 JA  IEEE Transactions on Computers ER   
Abstract—We propose an architecture for the computation of the doubleprecision floatingpoint multiplyaddfused (MAF) operation
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