This Article 
   
 Share 
   
 Bibliographic References 
   
 Add to: 
 
Digg
Furl
Spurl
Blink
Simpy
Google
Del.icio.us
Y!MyWeb
 
 Search 
   
Static Classification of Value Predictability Using Compiler Hints
August 2004 (vol. 53 no. 8)
pp. 929-944

Abstract—Predicting the values that are likely to be produced by instructions has been suggested as a way of increasing the instruction-level parallelism available in a superscalar processor. One of the potential difficulties in cost-effectively predicting values for a given instruction, however, is selecting the proper type of predictor, such as a last-value predictor, a stride predictor, or a context-based predictor. We propose a compiler-directed classification scheme that statically partitions all of the instructions in a program into several groups, each of which is associated with a specific value predictability pattern. This value predictability pattern is encoded into the instructions to identify the type of value predictor that will be best suited for predicting the values that are likely to be produced by each instruction at runtime. Both a profile-based compiler implementation and an implementation based on the GCC compiler are studied to show the performance bounds for the proposed technique. Our simulations using an extension to the SimpleScalar tool set and the SPEC95 and SPEC2000 benchmark programs indicate that this approach can efficiently use the limited hardware resources in superscalar processors. This static partitioning approach produces better performance than a dynamically partitioned approach and a simple round-robin distribution approach for a given hardware configuration. Finally, this work further demonstrates the connection between value locality behavior and source-level program structures, thereby leading to a deeper understanding of the causes of this behavior.

[1] F. Gabbay and A. Mendelson, The Effect of Instruction Fetch Bandwidth on Value Prediction Proc. 25th Int'l Symp. Computer Architecture, pp. 272-281, 1998.
[2] S. Lee, Y. Wang, and P. Yew, “Decoupled Value Prediction on Trace Processors,” Proc. Sixth Int'l Symp. High Performance Computer Architecture (HPCA-6), 2000.
[3] M.H. Lipasti and J.P. Shen, "Exceeding the Data-Flow Limit Via Value Prediction," Proc. 29th Ann. ACM/IEEE Int'l Symp. on Microarchitecture, IEEE CS Press, Los Alamitos, Calif., 1996, pp. 226-237.
[4] F. Gabbay and A. Mendelson, Speculative Execution Based on Value Prediction Electrical Eng. Dept. Technical Report 1080, Technion-Israel Inst. of Tech nology, Nov. 1996.
[5] Y. Sazeides and J. Smith, “The Predictability of Data Values,” Proc. 30th Ann. Int'l Symp. Microarchitecture (MICRO '30), pp. 248-258, Dec. 1997.
[6] K. Wang and M. Franklin, Highly Accurate Data Value Prediction Using Hybrid Predictors Proc. 30th Int'l Symp. Microarchitecture, 1997.
[7] B. Rychlik, J. Faistl, B. Krug, A. Kurland, J. Jung, M. Velev, and J. Shen, Efficient and Accurate Value Prediction Using Dynamic Classification technical report, Microarchitecture Research Team, Dept. of Electrical and Computer Eng., Carnegie Mellon Univ., 1998.
[8] B. Rychlik, J. Faistl, B. Krug, and J. Shen, “Efficacy and Performance Impact of Value Prediction,” Parallel Architectures and Compilation Techniques, Oct. 1998.
[9] Q. Zhao and D.J. Lilja, Compiler-Directed Classification of Value Locality Behavior Proc. Int'l Conf. Computer Design, Sept. 2001.
[10] D. Connors and W. Hwu, Compiler-Directed Dynamic Computation Reuse: Rationale and Initial Results Proc. 32nd Annual Int'l Symp. Microarchitecture, Nov. 1999.
[11] E. Larson and T. Austin, Compiler Controlled Value Prediction Using Branch Predictor Based Confidence Proc. 33rd Ann. ACM/IEEE Int'l Symp. Microarchitecture, Dec. 2000.
[12] S.S. Muchnick, Advanced Compiler Design Implementation. San Francisco: Morgan Kaufmann, 1997.
[13] A. Sodani and G. Sohi, An Empirical Analysis of Instruction Repetition Proc. Eighth Int'l Conf. Architectural Support for Programming Languages and Operating Systems, pp. 35-45, Oct. 1998.
[14] D. Burger, T. Austin, and S. Bennett, The Simplescalar Tool Set, Version 2.0 Technical Report 1342, Computer Science Dept., Univ. of Wisconsin, Madison, 1996.
[15] E. Rotenberg, S. Bennett, and J. Smith, "Trace Cache: A Low Latency Approach to High Bandwidth Instruction Fetching," Proc. 29th Ann. ACM/IEEE Int'l Symp. on Microarchitecture, IEEE CS Press, Los Alamitos, Calif., 1996, pp. 24-34.
[16] A.J. KleinOsowski, J. Flynn, N. Meares, and D.J. Lilja, Adapting the SPEC 2000 Benchmark Suite for Simulation-Based Computer Architecture Research Proc. Workshop Workload Characterization, Int'l Conf. Computer Design, Sept. 2000.
[17] Q. Zhao, S. Lee, and D.J. Lilja, Using Hyperprediction to Compensate for Delayed Updates in Value Predictors Laboratory for Advanced Research in Computing Technology and Compilers Technical Report No. ARCTiC 01-02, June 2001.
[18] T. Sato, Analyzing Overhead of Reissued Instructions on Data Speculative Processors Proc. Workshop Performance Analysis and Its Impaction on Design, 25th Int'l Symp. Computer Architecture, 1998.
[19] B. Calder, G. Reinman, and D. Tullsen, Selective Value Prediction Proc. 26th Int'l Symp. Computer Architecture, 1999.
[20] F. Gabbay and A. Mendelson, Can Program Profiling Support Value Prediction? Proc. 30th Int'l Symp. Microarchitecture, pp. 270-280, Dec. 1997.
[21] Y. Sazeides and J.E. Smith, “Modeling Program Predictability,” Proc. Int'l Symp. Computer Architecture, 1998.
[22] R.J. Eickemeyer and S. Vassiliadis, A Load Instruction Unit for Pipelined Processors IBM J. Research and Development, vol. 37, no. 4, pp. 547-564, July 1993.
[23] B. Calder, P. Feller, and A. Eustace, “Value Profiling,” Proc. 27th Ann. Int'l Symp. Microarchitecture (MICRO-97), pp. 259–269, Dec. 1997.
[24] T.H. Heil, Z. Smith, and J.E. Smith, “Improving Branch Predictors by Correlating on Data Values,” Proc. Int'l Symp. Microarchitecture, 1999.
[25] B. Goeman, H. Vandierendonck, and K. de Bosschere, Differential FCM: Increasing Value Prediction Accuracy by Improving Table Usage Efficiency Proc. Int'l Symp. High-Performance Computer Architecture, pp. 207-216, Jan. 2001.
[26] Y. Sazeides and J.E. Smith, Implementations of Context-Based Value Predictors Univ. of Wisconsin Technical Report ECE97-8, 1997.
[27] R. Bodik, Path-Sensitive Value-Flow Optimizations of Programs PhD dissertation, Univ. of Pittsburgh, Nov. 1999.
[28] M. Burtscher, A. Diwan, and M. Hauswirth, Static Load Classification for Improving the Value Predictability of Data-Cache Misses Proc. Conf. Programming Language Design and Implementation (PLDI), pp. 222-233, June 2002.

Index Terms:
Value prediction, value locality, compiler optimization, compiler heuristics, superscalar processors, computer architecture.
Citation:
Qing Zhao, David J. Lilja, "Static Classification of Value Predictability Using Compiler Hints," IEEE Transactions on Computers, vol. 53, no. 8, pp. 929-944, Aug. 2004, doi:10.1109/TC.2004.49
Usage of this product signifies your acceptance of the Terms of Use.