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CeRA: A Router for Symmetrical FPGAs Based on Exact Routing Density Evaluation
July 2004 (vol. 53 no. 7)
pp. 829-842

Abstract—This paper presents a new performance and routability driven routing algorithm for symmetrical array-based field-programmable gate arrays (FPGAs). A key contribution of our work is the overcoming of one essential limitation of the previous routing algorithms: inaccurate estimations of routing density that were too general for symmetrical FPGAs. To this end, we formulate an exact routing density calculation that is based on a precise analysis of the structure (switch block) of symmetrical FPGAs and utilize it consistently in global and detailed routings. With an introduction to the proposed accurate routing metrics, we describe a new routing algorithm, called cost-effective net-decomposition-based routing, which is fast and yet produces remarkable routing results in terms of both routability and net/path delays. We performed extensive experiments to show the effectiveness of our algorithm based on the proposed cost metrics.

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Index Terms:
FPGAs, routing algorithms, performance, routability, routing density.
Nak-Woong Eum, Taewhan Kim, Chong-Min Kyung, "CeRA: A Router for Symmetrical FPGAs Based on Exact Routing Density Evaluation," IEEE Transactions on Computers, vol. 53, no. 7, pp. 829-842, July 2004, doi:10.1109/TC.2004.20
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