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CeRA: A Router for Symmetrical FPGAs Based on Exact Routing Density Evaluation
July 2004 (vol. 53 no. 7)
pp. 829-842

Abstract—This paper presents a new performance and routability driven routing algorithm for symmetrical array-based field-programmable gate arrays (FPGAs). A key contribution of our work is the overcoming of one essential limitation of the previous routing algorithms: inaccurate estimations of routing density that were too general for symmetrical FPGAs. To this end, we formulate an exact routing density calculation that is based on a precise analysis of the structure (switch block) of symmetrical FPGAs and utilize it consistently in global and detailed routings. With an introduction to the proposed accurate routing metrics, we describe a new routing algorithm, called cost-effective net-decomposition-based routing, which is fast and yet produces remarkable routing results in terms of both routability and net/path delays. We performed extensive experiments to show the effectiveness of our algorithm based on the proposed cost metrics.

[1] The Programmable Gate Array Data Book. San Jose, Calif.: Xilinx Inc., 1992,
[2] H. Schmit and V. Chandra, FPGA Switch Block Layout and Evaluation Proc. ACM Symp. Field-Programmable Gate Array, pp. 11-18, 2002.
[3] S. Brown, J. Rose, and Z.G. Vranesic, “A Detailed Router for Field-Programmable Gate Arrays,” IEEE Trans. Computer-Aided Design, vol. 11, pp. 620-628, May 1992.
[4] F.D. Lewis and W.C.-C. Pong, A Negative Reinforcement Method for PGA Routing Proc. 30th Design Automation Conf., pp. 601-605, 1993.
[5] G.G. Lemieux and S.D. Brown, A Detailed Routing Algorithm for Allocating Wire Segments in Field-Programmable Gate Arrays Proc. ACM/SIGDA Physical Design Workshop, pp. 215-226, 1993.
[6] Y.-L. Wu and M. Marek-Sadowska, An Efficient Router for 2-D Field-Programmable Gate Arrays Proc. European Design and Test Conf., pp. 412-416, 1994.
[7] M.J. Alexander and G. Robins, New Performance-Driven FPGA Routing Algorithms Proc. 32nd Design Automation Conf., pp. 562-567, 1995.
[8] Y. Sun and C.L. Liu, Routing in a New 2-Dimensional FPGA/FPIC Routing Architecture Proc. 31th Design Automation Conf., pp. 171-176, 1994.
[9] Y. Sun, T.-C. Wang, C.K. Wong, and C.L. Liu, “Routing for Symmetric FPGAs and FPICs,” Proc. IEEE/ACM Int'l Conf. Computer-Aided Design, pp. 486-490, Santa Clara, Calif., Nov. 1993.
[10] T. Ohtsuki, Maze-Running and Line-Search Algorithm Layout and Design Verification, pp. 99-131, North-Holland, 1985.
[11] C.-D. Chen, Y.-S Lee, A.C.-H. Wu, and Y.-L. Lin, TRACER-fpga: A Router for RAM-Based FPGA's IEEE Trans. Computer-Aided Design, vol. 14, no. 3, pp. 371-374, Mar. 1995.
[12] Y.-S. Lee and A.C.-H. Wu, A Performance and Routability-Driven Router for FPGA's Considering Path Delays IEEE Trans. Computer-Aided Design, vol. 16, no. 2, pp. 179-185, Feb. 1997.
[13] N.-W. Eum, T. Kim, and C.-M. Kyung, A Router for Symmetrical FPGA Based on Exact Routing Density Evaluation Proc. Int'l Conf. Computer-Aided Design, pp. 137-143, 2001.
[14] J. Hu and S. Sapatnekar, Performance Driven Global Routing through Gradual Refinement Proc. Int'l Conf. Computer Design, pp. 481-483, 2001.
[15] J.S. Rose and S. Brown, "Flexibility of Interconnection Structures for Field-Programmable Gate Arrays," IEEE J. Solid-State Circuits, Vol. 26, No. 3, Mar. 1991, pp. 277-282.
[16] C.Y. Lee, An Algorithm for Path Connections and Its Application IRE Trans. Electronic Computers, vol. 10, pp. 346-365, Sept. 1961.
[17] T. Sadakane, H. Shirota, K. Takahashi, M. Terai, and K. Okazaki, A Congestion-Driven Placement Improvement Algorithm for Large Scale Sea-of-Gates Arrays Proc. Custom Integrated Circuit Conf., pp. 573-576, 1997.
[18] J. Lou, S. Krishnamoorthy, and H. Sheng, Estimating Routing Congestion Using Probabilistic Analysis Proc. Int'l Symp. Physical Design, pp. 112-117, 2001.
[19] M. Kubale and B. Jackowski, A Generalized Implicit Enumeration Algorithm for Graph Coloring Comm. ACM, vol. 28, no. 4, pp. 412-418, Apr. 1985.
[20] M.J. Alexander, J.P. Cohoon, J.L. Ganley, and G. Robins, Performance-Oriented Placement and Routing for Field-Programmable Gate Arrays Proc. European Design Automation Conf., 1995.
[21] Y.-L. Wu and M. Marek-Sadowska, Orthogonal Greedy Coupling A New Optimization Approach to 2-D FPGA Routing Proc. 32nd Design Automation Conf., pp. 568-573, 1995.
[22] G. Lemieux, S. Brown, and D. Vranesic, On Two-Step Routing for FPGAs Proc. Int'l Symp. Physical Design, pp. 60-66, 1997.
[23] V. Betz and J. Rose, VPR: A New Packing, Placement and Routing Tool for FPGA Research Proc. Seventh Int'l Workshop Field-Programmable Logic, pp. 213-222, 1997.
[24] S. Baase, Computer Algorithms Introduction to Design and Analysis. Addison-Wesley, 1988.

Index Terms:
FPGAs, routing algorithms, performance, routability, routing density.
Citation:
Nak-Woong Eum, Taewhan Kim, Chong-Min Kyung, "CeRA: A Router for Symmetrical FPGAs Based on Exact Routing Density Evaluation," IEEE Transactions on Computers, vol. 53, no. 7, pp. 829-842, July 2004, doi:10.1109/TC.2004.20
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