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Issue No.06 - June (2004 vol.53)
pp: 653-665
Oguz Ergin , IEEE
ABSTRACT
<p><b>Abstract</b>—All contemporary dynamically scheduled processors support register renaming to cope with false data dependencies. One of the ways to implement register renaming is to use the slots within the Reorder Buffer (ROB) as physical registers. In such designs, the ROB is a large multiported structure that occupies a significant portion of the die area and dissipates a sizable fraction of the total chip power. The heavily ported ROB is also likely to have a large delay that can limit the processor clock rate. We consider several approaches for reducing the ROB complexity in processors that use the ROB slots to implement physical registers. The first approach exploits the fact that the bulk of the source operand reads are satisfied through forwarding or reading of the committed register values. Our technique completely eliminates the read ports needed on the ROB for reading source operands. A small set of associatively addressed retention latches is used to compensate for the resulting performance degradation by caching the most recently produced results. The second technique relies on a distributed implementation that spreads the centralized ROB structure across the function units (FUs), with each distributed component sized to match the FU workload and with one write port and two read ports on each component. The third approach combines the use of retention latches and a distributed ROB implementation that uses minimally ported distributed components. The net result of combining the two techniques is the ROB distribution with minimal conflicts over the read and no conflicts over the write ports. Our designs are evaluated using the simulation of SPEC 2000 benchmarks and measurements of the actual ROB layouts in a 0.18 micron CMOS process.</p>
INDEX TERMS
Reorder buffer, complexity-effective design, low-power datapath, register file.
CITATION
Gurhan Kucuk, Dmitry V. Ponomarev, Oguz Ergin, Kanad Ghose, "Complexity-Effective Reorder Buffer Designs for Superscalar Processors", IEEE Transactions on Computers, vol.53, no. 6, pp. 653-665, June 2004, doi:10.1109/TC.2004.5
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