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An Effective Multilevel Algorithm for Bisecting Graphs and Hypergraphs
June 2004 (vol. 53 no. 6)
pp. 641-652

Abstract—Partitioning is a fundamental problem in diverse fields of study such as data mining, parallel processing, and the design of VLSI circuits. A new approach to partition graphs and hypergraphs is introduced. This new approach combines local and global sampling, clustering, and Tabu Search in a multilevel partitioning algorithm (TPART). TPART was implemented in a C program and compared to many state-of-the-art partitioning algorithms using a wide variety of benchmarks. TPART consistently performs well on the various benchmarks used and in comparison with other partitioning algorithms. TPART has a reasonably fast running time and it can produce a high quality partition of a graph of 262,144 nodes and 524,286 edges in less than 2 minutes CPU times on a Compaq Alpha DS20E 67/667 MHZ machine with 1GB of main memory.

[1] B. Hendrickson and R. Leland, An Improved Spectral Graph Partitioning Algorithm for Mapping Parallel Computations SIAM J. Scientific Computing, vol. 16, no. 2, pp. 452-469, 1995.
[2] C. Alpert and A. Kahng, Recent Directions in Netlist Partitioning: A Survey Integration-The VLSI J., vol. 19, nos. 1-2, pp. 1-81, 1995.
[3] F.M. Johannes, Partitioning of VLSI Circuits and Systems Proc. Design Automation Conf., pp. 83-87, 1996.
[4] C. Ding, H. Xiaofeng, Z. Hongyuan, G. Ming, and H. Simon, A Min-Max Cut Algorithm for Graph Partitioning and Data Clustering Proc. IEEE Int'l Conf. Data Mining, pp. 107-114, 2001.
[5] B.W. Kernighan and S. Lin, An Efficient Heuristic Procedure for Partitioning Graphs Bell System Technical J., vol. 49, pp. 291-307, Feb. 1970.
[6] C. Fiduccia and R. Mattheyses, A Linear-Time Heuristics for Improving Network Partitions Proc. 19th Design Automation Conf., pp. 175-181, Jan. 1982.
[7] M.R. Garey and D.S. Johnson, Computers and Intractability: A Guide to the Theory of NP-Completeness. New York: W.H. Freeman, 1979.
[8] T. Bui and C. Jones, Finding Good Approximate Vertex and Edge Partitions Is NP-Hard Information Processing Letters, vol. 42, pp. 153-159, 1992.
[9] R. Battiti and A. Bertossi, Greedy, Prohibition, and Reactive Heuristics for Graph Partitioning IEEE Trans. Computers, vol. 48, no. 4, pp. 361-385, Apr. 1999.
[10] Y.G. Saab, ”A Fast and Robust Network Bisection Algorithm,” IEEE Trans. Computers, vol. 44, no. 7, July 1995.
[11] Y. Saab, A New 2-Way Multi-Level Partitioning Algorithm VLSI Design J., vol. 11, no. 3, pp. 301-310, 2000.
[12] G. Karypis, R. Aggarwal, V. Kumar, and S. Shekar, Multilevel Hypergraph Partitioning: Applications in VLSI Domain Proc. ACM/IEEE Design Automation Conf., 1997.
[13] C.J. Alpert, J.-H. Huang, and A.B. Kahng, Multilevel Circuit Partitioning Proc. Design Automation Conf., pp. 530-533, 1997.
[14] J. Cong, H.P. LI, S.K. Lim, T. Shibuya, and D. Xu, Large Scale Circuit Partitioning with Loose/Stable Net Removal and Signal Flow Based Clustering Proc. Int'l Conf. Computer-Aided Design, pp. 441-446, 1997.
[15] M. Lee and Y. Kim, "PatchODMRP: An Ad Hoc Multicast Routing Protocol," Proc. 15th Int'l Conf. Information Networking (ICOIN 2001), IEEE CS Press, Los Alamitos, Calif., 2001, pp. 537-543.
[16] L.W. Hagen, D.J.H. Huang, and A.B. Kahng, On Implementation Choices for Iterative Improvement Partitioning Algorithms IEEE Trans. Computer-Aided Design, vol. 16, no. 10, pp. 1199-1205, 1997.
[17] T.N. Bui and B.R. Moon, Genetic Algorithm and Graph Partitioning IEEE Trans. Computers, vol. 45, no. 7, pp. 841-855, July 1996.
[18] D.S. Johnson, C.R. Aragon, L.A. McGeoch, and C. Schevon, Optimization by Simulated Annealing: An Experimental Evaluation; Part I, Graph Partitioning Operations Research, vol. 37, pp. 865-892, Nov.-Dec. 1989.
[19] T. Bui, S. Chaudhuri, T. Leighton, and M. Sipser, Graph Bisection Algorithm with Good Average Case Behavior Combinatorica, vol. 7, no. 2, pp. 171-191, 1987.
[20] B. Monien and R. Diekmann, A Local Graph Partitioning Heuristic Meeting Bisection Bounds Proc. Eighth SIAM Conf. Parallel Processing for Scientific Computing, 1997.
[21] I. Duff, R. Grimes, and J. Lewis, Sparse Matrix Test Problems ACM Trans. Math. Software, vol. 15, no. 1, pp. 1-14, 1989.
[22] C. Alpert, The ISPD98 Circuit Benchmarks Suite Proc. Physical Design Workshop, pp. 80-85, 1998.
[23] B. Hendrickson and R. Leland, The Chaco User's Guide Technical Report SAND94-2692, SANDIA Nat'l Laboratories, Albuquerque, N.M., 1994.
[24] G. Karypis and V. Kumar, A Fast and High Quality Multilevel Scheme for Partitioning Irregular Graphs Technical Report 95-035, Dept. of Computer Science Univ. of Minnesota, 1995.
[25] F. Pellegrini and J. Roman, Scotch: A Software Package for Static Mapping by Dual Recursive Bipartitioning of Process and Architecture Graphs Proc. European Int'l Conf. High Performance Computing and Networking (HPCN '96), pp. 493-498, Apr. 1996.
[26] R. Preis and R. Diekmann, The Party Partitioning Library, User Guide Technical Report TR-RSFB-96-024, Univ. of Paderborn, Germany, 1996.
[27] S. Dutt and W. Deng, VLSI Circuit Partitioning by Cluster-Removal Using Iterative Improvement Techniques Proc. Int'l Conf. Computer-Aided Design, pp. 194-200, 1996.

Index Terms:
Bisection, partitioning, iterative improvement, graph, hypergraph.
Youssef G. Saab, "An Effective Multilevel Algorithm for Bisecting Graphs and Hypergraphs," IEEE Transactions on Computers, vol. 53, no. 6, pp. 641-652, June 2004, doi:10.1109/TC.2004.3
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