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Partial Scan Design Based on Circuit State Information and Functional Analysis
March 2004 (vol. 53 no. 3)
pp. 276-287

Abstract—Partial scan design is divided into two stages: 1) critical cycle breaking and 2) partial scan flip-flop selection with respect to conflict resolution. A multiple phase partial scan design method is introduced by combining circuit state information and conflict analysis. Critical cycles are broken using a combination of valid circuit state information and conflict analysis. It is quite cost-effective to obtain circuit state information via logic simulation, therefore, circuit state information is iteratively updated after a given number of partial scan flip-flops have been selected. The valid-state-based testability measure may become ineffective to select scan flip-flops when cycles remaining in the circuit are not so influential to testability. The method turns to the conflict resolution process using an intensive conflict-analysis-based testability measure conflict. Sufficient experimental results are presented.

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Index Terms:
Valid state, partial scan design, invalid state, conflict, testability measure, testability improvement potential.
Citation:
Dong Xiang, Janak H. Patel, "Partial Scan Design Based on Circuit State Information and Functional Analysis," IEEE Transactions on Computers, vol. 53, no. 3, pp. 276-287, March 2004, doi:10.1109/TC.2004.1261835
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