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Dong Xiang, Janak H. Patel, "Partial Scan Design Based on Circuit State Information and Functional Analysis," IEEE Transactions on Computers, vol. 53, no. 3, pp. 276287, March, 2004.  
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@article{ 10.1109/TC.2004.1261835, author = {Dong Xiang and Janak H. Patel}, title = {Partial Scan Design Based on Circuit State Information and Functional Analysis}, journal ={IEEE Transactions on Computers}, volume = {53}, number = {3}, issn = {00189340}, year = {2004}, pages = {276287}, doi = {http://doi.ieeecomputersociety.org/10.1109/TC.2004.1261835}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }  
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TY  JOUR JO  IEEE Transactions on Computers TI  Partial Scan Design Based on Circuit State Information and Functional Analysis IS  3 SN  00189340 SP276 EP287 EPD  276287 A1  Dong Xiang, A1  Janak H. Patel, PY  2004 KW  Valid state KW  partial scan design KW  invalid state KW  conflict KW  testability measure KW  testability improvement potential. VL  53 JA  IEEE Transactions on Computers ER   
Abstract—Partial scan design is divided into two stages: 1) critical cycle breaking and 2) partial scan flipflop selection with respect to conflict resolution. A multiple phase partial scan design method is introduced by combining circuit state information and conflict analysis. Critical cycles are broken using a combination of valid circuit state information and conflict analysis. It is quite costeffective to obtain circuit state information via logic simulation, therefore, circuit state information is iteratively updated after a given number of partial scan flipflops have been selected. The validstatebased testability measure may become ineffective to select scan flipflops when cycles remaining in the circuit are not so influential to testability. The method turns to the conflict resolution process using an intensive conflictanalysisbased testability measure
[1] M. Abramovici, J.J. Kulikowski, and R.R. Roy, The Best FlipFlops to Scan Proc. IEEE Int'l Test Conf., pp. 166173, 1991.
[2] P. Ashar and S. Malik, Implicit Computation of MinimumCost Feedback Vertex Sets for Partial Scan and Other Applications Proc. ACM/IEEE Design Automation Conf., pp. 7780, 1994.
[3] V. Boppana and W.K. Fuchs, Partial Scan Design Based on State Transition Modeling Proc. IEEE Int'l Test Conf., pp. 538547, 1996.
[4] S.T. Chakradhar, A. Balakrishnan, and V.D. Agrawal, An Exact Algorithm for Selecting Partial Scan FlipFlops Proc. ACM/IEEE Design Automation Conf., pp. 8186, 1994.
[5] S.T. Chakradhar and S. Dey, Resynthesis and Retiming for Optimum Partial Scan Proc. 31st ACM/IEEE Design Automation Conf., pp. 8793, 1994.
[6] K.T. Cheng and V.D. Agrawal, Partial Scan Method for Sequential Circuits with Feedback IEEE Trans. Computers, vol. 39, pp. 544548, 1990.
[7] K.T. Cheng, SingleClock Partial Scan IEEE Design and Test of Computers, vol. 12, pp. 2431, Summer 1995.
[8] V. Chickermane and J.H. Patel, An Optimization Based Approach to the Partial Scan Design Problem Proc. IEEE Int'l Test Conf., pp. 377386, 1990.
[9] F. Corno, P. Prinetto, M. Sonza Reorda, and M. Violante, Exploiting Symbolic Techniques for Partial Scan FlipFlop Selection Proc. IEEE Design, Automation, and Test in Europe, 1998.
[10] R. Gupta, R. Gupta, and M.A. Breuer, The BALLAST Methodology for Structured Partial Scan Design IEEE Trans. Computers, vol. 39, pp. 538544, 1990.
[11] M. Hsiao, G.S. Saund, E.M. Rudnick, and J.H. Patel, Partial Scan Selection Based on Dynamic Reachability and Observability Information Proc. Int'l VLSI Design Conf., pp. 174180, 1998.
[12] N. Jiang, R.M. Chou, and K.K. Saluja, Synthesizing Finite State Machines for Minimum Length Synchronizing Sequence Using Partial Scan Proc. IEEE Int'l Symp. FaultTolerant Computing, pp. 4149, 1995.
[13] J.Y. Jou and K.T. Cheng, TimingDriven Partial Scan Proc. IEEE Int'l Conf. ComputerAided Design, pp. 404407, 1991.
[14] D. Kagaris and S. Tragoudas, RetimingBased Partial Scan IEEE Trans. Computers, vol. 45, no. 1, pp. 7487, Jan. 1996.
[15] P. Kalla and M.J. Ciesielski, A Comprehensive Approach to the Partial Scan Problem Using Implicit State Enumeration Proc. IEEE Int'l Test Conf., pp. 651657, 1998.
[16] P. Kalla and M.J. Ciesielski, A Comprehensive Approach to the Partial Scan Problem Using Implicit State Enumeration IEEE Trans. ComputerAided Design of Integrated Circuits and Systems, vol. 21, no. 7, pp. 810826, 2002.
[17] K. Kim and C. Kime, Partial Scan by Use of Empirical Testability Proc. IEEE Int'l Conf. ComputerAided Design, pp. 314317, 1990.
[18] A. Kunzmann and H.J. Wunderlich, An Analytical Approach to the Partial Scan Design Problem J. Electronic Testing: Theory and Applications, vol. 1, pp. 163174, 1990.
[19] D.H. Lee and S.M. Reddy, On Determining Scan FlipFlops in Partial Scan Designs Proc. IEEE/ACM Int'l Conf. ComputerAided Design, pp. 322325, 1990.
[20] H.C. Liang and C.L. Lee, Effective Methodology for Mixed Scan and Reset Design Based on Test Generation and Structure of Sequential Circuits Proc. Eighth IEEE Asian Test Symp., pp. 173178, 1999.
[21] X. Lin, I. Pomeranz, and S.M. Reddy, Full Scan Fault Coverage with Partial Scan Proc. IEEE Design, Automation, and Test in Europe, pp. 468472, 1999.
[22] T.E. Marchok, A.E. Maleh, W. Maly, and J. Rajski, Complexity of Sequential ATPG Proc. European Design&Test Conf., pp. 252261, 1995.
[23] S. Narayanan, R. Gupta, and M.A. Breuer, "Optimal Configuring of Multiple Scan Chains," IEEE Trans. Computers, vol. 42, no. 9, Sept. 1993, pp. 11211131.
[24] T. Niermann and J. Patel, HITEC: A Test Generation Package for Sequential Circuits Proc. European Conf. Design Automation, pp. 214218, 1991.
[25] P.S. Parihk and M. Abramovici, TestabilityBased Partial Scan Analysis J. Electronic Testing: Theory and Applications, vol. 7, pp. 4760, Aug. 1995.
[26] I. Park, D.S. Ha, and G. Sim, A New Method for Partial Scan Design Based on Propagation and Justification Requirements of Faults Proc. IEEE Int'l Test Conf., pp. 413422, 1995.
[27] S. Park, A Partial Scan Design Unifying Structural Analysis and Testabilities Int'l J. Electronics, vol. 88, no. 12, pp. 12371245, 2001.
[28] I. Pomeranz and S.M. Reddy, LOCSTEP: A Logic SimulationBased Test Generation Procedure Proc. IEEE Int'l Symp. FaultTolerant Computing, pp. 110118, 1995.
[29] G.S. Saund, M.S. Hsiao, and J.H. Patel, Partial Scan beyond Cycle Cutting Proc. IEEE Int'l Symp. FaultTolerant Computing, pp. 320328, 1997.
[30] S. Sharma and M. Hsiao, Combination of Structural and State Analysis for Partial Scan Proc. Int'l VLSI Design Conf., pp. 134139, Jan. 2001.
[31] S.E. Tai and D. Bhattacharya, A Three Stage Partial Scan Design Method to Ease ATPG J. Electronic Testing: Theory and Applications, vol. 7, pp. 95104, Nov. 1995.
[32] E. Trischler, Incomplete Scan Path with an Automatic Test Generation Methodology Proc. IEEE Int'l Test Conf., pp. 153162, 1980.
[33] D. Xiang, S. Venkataraman, W.K. Fuchs, and J.H. Patel, Partial Scan Design Based on Circuit State Information Proc. ACM/IEEE Design Automation Conf., pp. 807812, June 1996.
[34] D. Xiang and J.H. Patel, A Global Algorithm for the Partial Scan Design Problem Using Circuit State Information Proc. IEEE Int'l Test Conf., pp. 548557, Oct. 1996.
[35] D. Xiang, Y. Xu, and H. Fujiwara, NonScan Design for Testability for Synchronous Sequential Circuits Based on Conflict Analysis Proc. IEEE Int'l Test Conf., pp. 520529, 2000.