Test Access Mechanism Optimization, Test Scheduling, and Tester Data Volume Reduction for System-on-Chip
Issue No.12 - December (2003 vol.52)
Krishnendu Chakrabarty , IEEE
Vikram Iyengar , IEEE
<p><b>Abstract</b>—We describe an integrated framework for system-on-chip (SOC) test automation. Our framework is based on a new test access mechanism (TAM) architecture consisting of flexible-width test buses that can fork and merge between cores. Test wrapper and TAM cooptimization for this architecture is performed by representing core tests using rectangles and by employing a novel rectangle packing algorithm for test scheduling. Test scheduling is tightly integrated with TAM optimization and it incorporates precedence and power constraints in the test schedule, while allowing the SOC integrator to designate a group of tests as preemptable. Test preemption helps avoid hardware and power consumption conflicts, thereby leading to a more efficient test schedule. Finally, we study the relationship between TAM width and tester data volume to identify an effective TAM width for the SOC. We present experimental results on our test automation framework for four benchmark SOCs.</p>
Core-based systems, rectangle packing, system-on-a-chip, test access mechanism, test scheduling, testing time, test wrapper.
Krishnendu Chakrabarty, Vikram Iyengar, "Test Access Mechanism Optimization, Test Scheduling, and Tester Data Volume Reduction for System-on-Chip", IEEE Transactions on Computers, vol.52, no. 12, pp. 1619-1632, December 2003, doi:10.1109/TC.2003.1252857