
This Article  
 
Share  
Bibliographic References  
Add to:  
Digg Furl Spurl Blink Simpy Del.icio.us Y!MyWeb  
Search  
 
ASCII Text  x  
Mitrajit Chatterjee, Dhiraj K. Pradhan, "A BIST Pattern Generator Design for NearPerfect Fault Coverage," IEEE Transactions on Computers, vol. 52, no. 12, pp. 15431558, December, 2003.  
BibTex  x  
@article{ 10.1109/TC.2003.1252851, author = {Mitrajit Chatterjee and Dhiraj K. Pradhan}, title = {A BIST Pattern Generator Design for NearPerfect Fault Coverage}, journal ={IEEE Transactions on Computers}, volume = {52}, number = {12}, issn = {00189340}, year = {2003}, pages = {15431558}, doi = {http://doi.ieeecomputersociety.org/10.1109/TC.2003.1252851}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }  
RefWorks Procite/RefMan/Endnote  x  
TY  JOUR JO  IEEE Transactions on Computers TI  A BIST Pattern Generator Design for NearPerfect Fault Coverage IS  12 SN  00189340 SP1543 EP1558 EPD  15431558 A1  Mitrajit Chatterjee, A1  Dhiraj K. Pradhan, PY  2003 KW  Linear feedback shift registers KW  builtin selftest KW  scan KW  synthesis KW  test pattern generation KW  fault coverage KW  core logic KW  SOC. VL  52 JA  IEEE Transactions on Computers ER   
Abstract—A new design methodology for a pattern generator is proposed, formulated in the context of onchip BIST. The design methodology is circuitspecific and uses synthesis techniques to design BIST generators. The pattern generator consists of two components: a pseudorandom pattern generator (like an LFSR or, preferably, a GLFSR) and a combinational logic to map the outputs of the pseudorandom pattern generator. This combinational logic is synthesized to produce a given set of target patterns by mapping the outputs of the pseudorandom pattern generator. It is shown that, for a particular CUT, an areaefficient combinational logic block can be designed/synthesized to achieve 100 (or almost 100) percent single stuckat fault coverage using a small number of test patterns. This method is significantly different from weighted pattern generation and can guarantee testing of all hardtodetect faults without expensive test point insertion. Experimental results on common benchmark netlists demonstrate that the fault coverage of the proposed pattern generator is significantly higher compared to conventional pattern generation techniques. The design technique for the logic mapper is unique and can be used effectively to improve existing pattern generators for combinational logic and scanbased BIST structures.
[1] P.H. Bardell, W.H. McAnney, and J. Savir, BuiltIn Test for VLSI, John Wiley&Sons, New York, 1987.
[2] M. Abramovichi, M.A. Breuer, and A.D. Friedman, Digital Testing and Testable Design. Compter Science Press, 1993.
[3] M. Bershteyn, Calculation of Multiple Sets of Weights for Weighted Random Testing Proc. Int'l Test Conf., pp. 10311040, 1993.
[4] F. Muradali, V.K. Agarwal, and B. NadeauDostie, A New Procedure for Weighted Random BuiltInSelfTest Proc. Int'l Test Conf., pp. 660668, 1990,
[5] J.A. Waicukauski and E. Lindbloom, Fault Detection Effectiveness of Weighted Random Patterns Proc. Int'l Test Conf., pp. 245261, 1988.
[6] M.A. Miranda et al., Generation of Optimized Single Distributions of Weights for Random BIST Proc. Int'l Test Conf., pp. 10231030, 1993.
[7] J. Hartmann and G. Kemnitz, How to Do Weighted Random Testing for BIST Proc. Int'l Conf. ComputerAided Design (ICCAD), 1993.
[8] F. Saivoshi, WTPGA: A Novel Weighted Test Pattern Generation Approach for VLSI BIST Proc. Int'l Test Conf., pp. 256262, 1988.
[9] H. Wunderlich, Multiple Distributions of Biased Random Test Patterns IEEE Trans. ComputerAided Design, vol. 9, no. 6, June 1990.
[10] M. AlShaibi and C. Kime, FixedBiased Pseudorandom BIST for RandomPatternResistant Circuits Proc. Int'l Test Conf., pp. 929938, 1994.
[11] M. Cogswell, D. Pearl, J. Sage, and A. Troidl, Test Structure Verification of Logical BIST: Problems and Solutions Proc. Int'l Test Conf., pp. 123129, 2000.
[12] G. Kiefer and H.J. Wunderlich, Deterministic BIST with Multiple Scan Chains J. Electronic Testing: Theory and Applications (JETTA), pp. 8593, Feb.Apr. 1999.
[13] G. Hetherington, T. Fryars, N. Tamarapalli, M. Kassab, A. Hassan, and J. Rajski, Logic BIST for Large Industrial Designs: Real Issues and Case Studies Proc. Int'l Test Conf., pp. 358367, 1999.
[14] G. Kiefer, H. Vranken, E.J. Marinissen, and H.J. Wunderlich, Application of Deterministic Logic BIST on Industrial Circuits Proc. Int'l Test Conf., pp. 105114, 2000.
[15] D. Das and N.A. Touba, Reducing Test Data Volume Using External/LBIST Hybrid Test Patterns Proc. Int'l Test Conf., pp. 115122, 2000.
[16] V.K. Agarwal and E. Cerny, Store and Generate Builtin Testing Approach Proc. Int'l FaultTolerant Computing Symp. (FTCS 11), pp. 3540, June 1981.
[17] B. Vasudevan et al., LFSR Based Deterministic Hardware for AtSpeed BIST Proc. VLSI Test Symp., pp. 201207, 1992.
[18] D.A. Forsyth and J. Ponce, Computer Vision: A Modern Approach. Prentice Hall, 2002.
[19] J.V. Sas, F. Catthoor, and H.D. Man, Optimized BIST Strategies for Programmable Data Paths Based on Cellular Automata Proc. Int'l Test Conf., pp. 110119, 1992.
[20] S. Venkataraman et al., A Efficient BIST Scheme Based on Reseeding of Multiple Polynomial LFSRs Proc. Int'l Conf. ComputerAided Design (ICCAD), 1993.
[21] S. Boubezari and B. Kaminska, Cellular Automata Synthesis Based on PreComputed Test Vectors for BIST Proc. Int'l Conf. ComputerAided Design (ICCAD), 1993.
[22] S. Pateras and J. Rajski, CubeContained Random Patterns and Their Application to the Complete Testing of Synthesized MultiLevel Circuits Proc. Int'l Test Conf., pp. 473481, 1991.
[23] S. Akers and W. Jansz, Test Set Embedding in a BIST Environment Proc. Int'l Test Conf., pp. 257263, 1989.
[24] M. Chatterjee and D.K. Pradhan, A Novel Pattern Generator for NearPerfect Fault Coverage Proc. IEEE VLSI Test Symp., 1995.
[25] D.K. Pradhan and M. Chatterjee, GLFSR A New PseudoRandom Pattern Generator for BIST Proc. Int'l Test Conf., pp. 481490, 1994.
[26] D.K. Pradhan and S. Gupta, A New Framework for Designing and Analyzing BIST Techniques and Zero Aliasing Compression IEEE Trans. Computers, vol. 40, no. 6, June 1991.
[27] C. Dufaza et al., BIST Hardware Generator for Mixed Test Scheme Proc. European Design and Test Conf., 1995.
[28] C.H. Chen and S.K. Gupta, A Methodology to Design Efficient BIST Test Pattern Generators Proc. Int'l Test Conf., pp. 814823, 1995.
[29] W. Kunz and D.K. Pradhan, Recursive Learning: A New Implication Technique for Efficient Solution to CAD Problems Test, Verification and Optimization IEEE Trans. ComputerAided Design, pp. 11431158, Sept. 1994.
[30] M.R. Garey and D.S. Johnson, Computers and Intractability: A Guide to the Theory of NPCompleteness.New York: W.H. Freeman, 1979.
[31] P.H. Bardell, Analysis of Cellular Automata Used as a PseudoRandom Pattern Generators Proc. Int'l Test Conf., pp. 762768, 1990.
[32] P.D. Hortensius, R.D. McLeod, and H.C. Card, Parallel Random Number Generation for VLSI Systems using Cellular Automata IEEE Trans. Computers, vol. 38, no. 10, pp. 14661473, Oct. 1989.
[33] E.J. McCluskey, Verification Testing A Pseudoexhaustive Test Technique IEEE Trans. Computers, vol. 33, no. 6, pp. 541546, June 1984.
[34] G. De Micheli, Synthesis and Optimization of Digital Circuits. McGrawHill, 1994.
[35] F. Brglez and H. Fujiwara, A Neural Netlist of Ten Combinational Benchmark Circuits and a Target Translator in FORTRAN Proc. Int'l Symp. Circuits and Systems, June 1985.
[36] N. Touba and E.J. McCluskey, Transformed PseudoRandom Patterns for BIST Proc. IEEE VLSI Test Symp., 1995.
[37] N. Touba and E.J. McCluskey, Synthesis of Mapping Logic for Generating Transformed PseudoRandom Patterns for BIST Proc. Int'l Test Conf., pp. 674682, 1995.
[38] N. Touba and E.J. McCluskey, BitFixing in Pseudorandom Sequences for Scan BIST IEEE Trans. ComputerAided Design, vol. 20, no. 4, pp 545555, Apr. 2001.
[39] C. Krishna, A. Jas, and N. Touba, Test Vector Encoding Using Partial LFSR Reseeding Proc. Int'l Test Conf., pp. 884893, Oct. 2001.
[40] C. Fagot, O. Gascuel, P. Girard, and C. Landrault, A Ring Architecture Strategy for BIST Test Pattern Generation Proc. IEEE Seventh Asian Test Symp., pp. 418423, 1998.
[41] C. Fagot, P. Girard, and C. Landrault, On Using Machine Learning for Logic BIST Proc. Int'l Test Conf., pp. 338346, 1997.
[42] H. Liang, S. Hellebrand, and H.J. Wunderlich, Two Dimensional Test Data Compression for ScanBased Deterministic BIST Proc. Int'l Test Conf., pp. 894902, Oct. 2001.
[43] Y.K. Malaiya and S. Yang, A Coverage Problem for Random Testing Proc. IEEE Int'l Test Conf., pp. 237245, Nov. 1984.
[44] C.H. Chiang and S.K. Gupta, Random Pattern Testable Logic Synthesis Proc. Int'l Conf. ComputerAided Design, pp. 125128, Nov. 1994.
[45] M. Chatterjee, D.K. Pradhan, and W. Kunz, LOT: Logic Optimization with Testability New Transformations for Logic Synthesis IEEE Trans. ComputerAided Design, vol. 17, no. 5, pp. 386399, May 1998.
[46] Z. Zhao, B. Pouya, and N.A. Touba, BETSY: Synthesizing Circuits for a Specified BIST Environment Proc. Int'l Test Conf., pp. 144153, Oct. 1998.
[47] D.K. Pradhan and M. Chatterjee, GLFSR A New Test Pattern Generator for BuiltInSelfTest IEEE Trans. ComputerAided Design, vol. 18, no. 2, pp. 238247, Feb. 1999.