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Issue No.11 - November (2003 vol.52)
pp: 1495-1500
ABSTRACT
<p><b>Abstract</b>—We introduce a new PLA-based decoder architecture for random-access runtime decompression of compressed instruction memory in embedded systems. The compression method employs class-based coding. The symbol codebook used for decompression is fully programmable; thus, good compression may be achieved by adapting the codebook to the symbol frequency statistics of the target binary program. We show that this new class-based decoder architecture can be extended to provide high throughput decompression.</p>
INDEX TERMS
Embedded processors, code compression, decompressor architecture.
CITATION
Shlomo Weiss, Shay Beren, "Class-Based Decompressor Design for Compressed Instruction Memory in Embedded Processors", IEEE Transactions on Computers, vol.52, no. 11, pp. 1495-1500, November 2003, doi:10.1109/TC.2003.1244947
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