This Article 
 Bibliographic References 
 Add to: 
On Synthesis of Easily Testable (k, K) Circuits
November 2003 (vol. 52 no. 11)
pp. 1490-1494

Abstract—A (k,K) circuit is one which can be decomposed into nonintersecting blocks of gates where each block has no more than K external inputs, such that the graph formed by letting each block be a node and inserting edges between blocks if they share a signal line, is a partial k-tree. (k,K) circuits are special in that they have been shown to be testable in time polynomial in the number of gates in the circuit, and are useful if the constants k and K are small. We demonstrate a procedure to synthesise (k,K) circuits from a special class of Boolean expressions.

[1] S. Arnborg and A. Proskurowski, Linear Time Algorithms for NP-Hard Problems Restricted to Partial k-Trees Discrete Applied Math., vol. 23, pp. 11-24, 1989.
[2] S. Arnborg, D.G. Corneil, and A. Proskurowski, Complexity of Finding Embeddings in a k-Tree SIAM J. Algebraic and Discrete Methods, vol. 8, no. 2, pp. 277-284, Apr. 1987.
[3] S.T. Chakradhar, V.D. Agrawal, and M.L. Bushnell, Neural Models and Algorithms for Digital Testing: Dordrecht, The Netherlands, Kluwer Academic Publishers, 1991.
[4] H. Fujiwara and S. Toida, The Complexity of Fault Detection Problems for Combinational Logic Circuits IEEE Trans. Computers, vol. 31, no. 6, pp. 553-560, June 1982.
[5] E. Korach and N. Solel, Treewidth, Pathwidth and Cutwidth Discrete Applied Math., vol. 43, pp. 97-101, 1993.
[6] J. van Leeuwen, Graph Algorithms Handbook of Theoretical Computer Science, Volume A: Algorithms and Complexity Theory, pp. 527-631. Amsterdam: North Holland Publishing, 1990.
[7] S.R. Naidu, Polynomial-Time Testable Combinational Circuits MSc (Engg) thesis, Dept. of Computer Science and Automation, Indian Inst. of Science, July 1998.
[8] M.R. Prasad, P. Chong, and K. Keutzer, Why Is ATPG Easy? Proc. 36th Design Automation Conf., pp. 22-28, 1999.
[9] N.S.V. Rao and S. Toida, On Polynomial-Time Testable Combinational Circuits IEEE Trans. Computers, vol. 43, no. 11, pp. 1298-1309, Nov. 1994.
[10] N.D. Robertson and P.D. Seymour, Graph Minors III. Planar Tree-Width J. Combinatorial Theory, Series B 36, pp. 49-64, 1984.

Index Terms:
Testing, stuck-at fault, polynomial time, k-tree, treewidth, synthesis.
Srinath R. Naidu, Vijay Chandru, "On Synthesis of Easily Testable (k, K) Circuits," IEEE Transactions on Computers, vol. 52, no. 11, pp. 1490-1494, Nov. 2003, doi:10.1109/TC.2003.1244946
Usage of this product signifies your acceptance of the Terms of Use.