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Issue No.11 - November (2003 vol.52)
pp: 1470-1479
ABSTRACT
<p><b>Abstract</b>—This work addresses the problem of predicting the yield of a chip composed of cores. A center-satellite model is used to directly represent observed spatial autocorrelation of integrated circuit spot defects. This model is compared to another (large-area clustering) model that only indirectly represents intrawafer correlation. We illustrate that, when different portions of a chip have different susceptibility to defects, the chip layout will affect the predicted yield. This is particularly relevant when portions of a chip are defect-tolerant because their susceptibility to defects is dramatically different. We illustrate how the yield models can be used to predict the utility of making much of a chip (or an embedded core) defect-tolerant. Two yield points parameterized the models. The one extra parameter of, and the suitability of, the center-satellite model allowed it to track the yield data points with less than 1/10,000 of the error of the large-area clustering model. However, the simpler large-area clustering model is accurate in some circumstances, especially when the chip area is small.</p>
INDEX TERMS
Yield, defect tolerance, integrated circuit, embedded core.
CITATION
Fred J. Meyer, "Predicting Defect-Tolerant Yield in the Embedded Core Context", IEEE Transactions on Computers, vol.52, no. 11, pp. 1470-1479, November 2003, doi:10.1109/TC.2003.1244944
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