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CMOS VLSI Implementation of a Low-Power Logarithmic Converter
November 2003 (vol. 52 no. 11)
pp. 1421-1433

Abstract—This paper presents a unique 32-bit binary-to-binary logarithm converter including its CMOS VLSI implementation. The converter is implemented using combinational logic only and it calculates a logarithm approximation in a single clock cycle. Unlike other complex logarithm correcting algorithms, three unique algorithms are developed and implemented with low-power and fast circuits that reduce the maximum percent errors that result from binary-to-binary logarithm conversion to 0.9299 percent, 0.4314 percent, and 0.1538 percent. Fast 4, 16, and 32-bit leading-one detector circuits are designed to obtain the leading-one position of an input binary word. A 32-word x 5-bit MOS ROM is used to provide 5-bit integers based on the corresponding leading-one position. Both converter area and speed have been considered in the design approach, resulting in the use of a very efficient 32-bit logarithmic shifter in the 32--bit logarithmic converter. The converter is implemented using 0.6\mu{\rm m} CMOS technology, and it requires 1,600\lambda\times 2,800\lambda of chip area. Simulations of the CMOS design for the 32-bit logarithmic converter, operating at {\rm V_{DD}} equal to 5 volts, run at 55 MHz, and the converter consumes 20 milliwatts.

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Index Terms:
Anti-logarithm, binary logarithms, elementary functions, floating-point normalization, logarithmic number system, leading-one detector, low-power circuits.
Citation:
Khalid H. Abed, Raymond E. Siferd, "CMOS VLSI Implementation of a Low-Power Logarithmic Converter," IEEE Transactions on Computers, vol. 52, no. 11, pp. 1421-1433, Nov. 2003, doi:10.1109/TC.2003.1244940
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