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Khalid H. Abed, Raymond E. Siferd, "CMOS VLSI Implementation of a LowPower Logarithmic Converter," IEEE Transactions on Computers, vol. 52, no. 11, pp. 14211433, November, 2003.  
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@article{ 10.1109/TC.2003.1244940, author = {Khalid H. Abed and Raymond E. Siferd}, title = {CMOS VLSI Implementation of a LowPower Logarithmic Converter}, journal ={IEEE Transactions on Computers}, volume = {52}, number = {11}, issn = {00189340}, year = {2003}, pages = {14211433}, doi = {http://doi.ieeecomputersociety.org/10.1109/TC.2003.1244940}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }  
RefWorks Procite/RefMan/Endnote  x  
TY  JOUR JO  IEEE Transactions on Computers TI  CMOS VLSI Implementation of a LowPower Logarithmic Converter IS  11 SN  00189340 SP1421 EP1433 EPD  14211433 A1  Khalid H. Abed, A1  Raymond E. Siferd, PY  2003 KW  Antilogarithm KW  binary logarithms KW  elementary functions KW  floatingpoint normalization KW  logarithmic number system KW  leadingone detector KW  lowpower circuits. VL  52 JA  IEEE Transactions on Computers ER   
Abstract—This paper presents a unique 32bit binarytobinary logarithm converter including its CMOS VLSI implementation. The converter is implemented using combinational logic only and it calculates a logarithm approximation in a single clock cycle. Unlike other complex logarithm correcting algorithms, three unique algorithms are developed and implemented with lowpower and fast circuits that reduce the maximum percent errors that result from binarytobinary logarithm conversion to 0.9299 percent, 0.4314 percent, and 0.1538 percent. Fast 4, 16, and 32bit leadingone detector circuits are designed to obtain the leadingone position of an input binary word. A 32word x 5bit MOS ROM is used to provide 5bit integers based on the corresponding leadingone position. Both converter area and speed have been considered in the design approach, resulting in the use of a very efficient 32bit logarithmic shifter in the 32bit logarithmic converter. The converter is implemented using
[1] J.N. Mitchell Jr., Computer Multiplication and Division Using Binary Logarithms IRE Trans. Electronic Computers, vol. 11, pp. 512517, Aug. 1962.
[2] M. Combet, H. Zonneveld, and L. Verbeek, Computation of the Base Two Logarithm of Binary Numbers IEEE Trans. Electronic Computers, vol. 14, pp. 863867, Dec. 1965.
[3] E.L. Hall, D.D. Lynch, and S.J. Dwyer III, Generation of Products and Quotients Using Approximate Binary Logarithms for Digital Filtering Applications IEEE Trans. Computers, vol. 19, pp. 97105, Feb. 1970.
[4] S.L. SanGregory, R.E. Siferd, C. Brother, and D. Gallagher, A Fast, LowPower Logarithm Approximation with CMOS VLSI Implementation Proc. IEEE Midwest Symp. Circuits and Systems, Aug. 1999.
[5] J.M. Muller, Elementary Functions. Algorithms and Implementation. Birkhauser, 1997.
[6] W.F. Wong and E. Goto, “Fast HardwareBased Algorithms for Elementary Function Computations,” IEEE Trans. Computers, vol. 43, no. 3, pp. 278294, Mar. 1994.
[7] M.J. Schulte and E.E. Swartzlander Jr., Hardware Designs for Exactly Rounded Elementary Functions IEEE Trans. Computers, vol. 43, no. 8, pp. 964973, Aug. 1994.
[8] K.H. Abed and R.E. Siferd, CMOS VLSI Implementation of 16Bit Logarithm and AntiLogarithm Converters Proc. IEEE Midwest Symp. Circuits and Systems, Aug. 1999.
[9] M. Schmookler and K. Nowka, Leading Zero Anticipation and Detection A Comparison of Methods, Proc. 15th IEEE Symp. Computer Arithmetic, pp. 712, 2001.
[10] V. Oklobdzija, An Implementation Algorithm and Design of a Novel Leading Zero Detector Circuit Proc. 26th IEEE Asilomar Conf. Signals, Systems, and Computers, pp. 391395, 1992.
[11] V.G. Oklobdzija, “An Algorithmic and Novel Design of a Leading Zero Detector Circuit: Comparison with Logic Synthesis,” IEEE Trans. VLSI Systems, vol. 2, no. 1, pp. 124128, 1994.
[12] V. Oklobdzija, Comments on LeadingZero Anticipatory Logic for HighSpeed Floating Point Addition IEEE J. SolidState Circuits, pp. 292293, 1997.
[13] M. Schmookler and D. Mikan, TwoState Leading Zero/One Anticipator (LZA) US Patent #5493520, Feb. 1996.
[14] H. Suzuki, H. Morinaka, H. Makino, Y. Nakase, K. Mashiko, and T. Sumi, “LeadingZero Anticipatory Logic for High Speed Floating Point Addition,” IEEE J. SolidState Circuits, vol. 31, no. 8, pp. 1,1571,164, 1996.
[15] J.D. Bruguera and T. Lang, “LeadingOne Prediction Scheme for Latency Improvement in Single Datapath FloatingPoint Adders,” Proc. Int'l Conf. Computer Design (ICCD'98), pp. 298305, 1998.
[16] J. Bruguera and T. Lang, LeadingOne Prediction with Concurrent Position Correction IEEE Trans. Computers, vol. 48, no. 10, pp. 298305, Oct. 1999.
[17] G.P. Frangakis, A New Binary Logarithm Based Computing System Proc. IEE, pp. 169173, Sept. 1983.
[18] B. Hoefflinger, Efficient VLSI Digital Logarithmic CODECS Electronics Letters, pp. 11321134, June 1991.
[19] G.P. Frangakis, Fast Binary Logarithm Computing Circuit for Binary Numbers Less than One Electronics Letters, pp. 574575, July 1980.
[20] J.F. Wakerly, Digital Design: Principle and Practices. Prentice Hall, 1994.
[21] B. Bailey, BarrelShifter IC Manipulates Up to 32Bits Electronic Design, pp. 385391, Jan. 1984.
[22] G.M. Tharakan and S.M. Kang, A New Design of a Fast Barrel Switch Network IEEE J. SolidState Circuits, pp. 217221, Feb. 1992.
[23] R. Pereira, J.A. Michell, and J.M. Solana, Fully Pipelined TSPC Barrel Shifter for High Speed Applications IEEE J. SolidState Circuits, pp. 686690, June 1995.
[24] S.J. Yih, M. Cheng, and W.S. Feng, Multilevel Barrel Shifter for CORDIC Design Electronic Letters, pp. 11781179, June 1996.
[25] J.M. Rabaey, Digital Integrated CircuitsUpper Saddle River, N.J.: Prentice Hall, 1996.
[26] V. Paliouras and T. Stouraitis, LowPower Properties of the Logarithmic Number System Proc. 15th IEEE Symp. Computer Arithmetic, pp. 229236, June 2001.