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Modulo 2n ± 1 Adder Design Using Select-Prefix Blocks
November 2003 (vol. 52 no. 11)
pp. 1399-1406

Abstract—In this paper, we present new design methods for modulo 2n± 1 adders. We use the same select-prefix addition block for both modulo 2n - 1 and diminished-one modulo 2^n+1 adder design. VLSI implementations of the proposed adders in static CMOS show that they achieve an attractive combination of speed and area costs.

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Index Terms:
modulo 2n± 1 adders, select-prefix adders, computer arithmetic, VLSI architectures.
Costas Efstathiou, Haridimos T. Vergos, Dimitris Nikolos, "Modulo 2n ± 1 Adder Design Using Select-Prefix Blocks," IEEE Transactions on Computers, vol. 52, no. 11, pp. 1399-1406, Nov. 2003, doi:10.1109/TC.2003.1244938
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