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Modulo 2n ± 1 Adder Design Using Select-Prefix Blocks
November 2003 (vol. 52 no. 11)
pp. 1399-1406

Abstract—In this paper, we present new design methods for modulo 2n± 1 adders. We use the same select-prefix addition block for both modulo 2n - 1 and diminished-one modulo 2^n+1 adder design. VLSI implementations of the proposed adders in static CMOS show that they achieve an attractive combination of speed and area costs.

[1] M.A. Soderstrand,W.K. Jenkins,G.A. Jullien,, and F.J. Taylor,Residue Number System Arithmetic: Modern Applicationsin Digital Signal Processing. IEEE Press, 1986.
[2] M.A. Bayoumi, G.A. Jullien, and W.C. Miller, “A Look-Up Table VLSI Design Methodology for RNS Structures Used in DSP Applications,” IEEE Trans. Circuits and Systems, vol. 34, pp. 604-616, June 1987.
[3] K. Elleithy and M. Bayoumi, “Fast and Flexible Architectures for RNS Arithmetic Decoding,” IEEE Trans. Circuits and Systems-II: Analog and Digital Signal Processing, vol. 39, pp. 226-235, Apr. 1992.
[4] I. Koren, Computer Arithmetic Algorithms.Englewood Cliffs, N.J.: Prentice Hall, 1993.
[5] W.K. Jenkins and B.J. Leon, "The Use of Residue Number Systems in the Design of Finite Impulse Response Digital Filters," IEEE Trans. Circuits and Systems, vol. 24, pp. 191-201, Apr. 1977.
[6] T.R.N. Rao and Fujiwara, Error-Coding for Computer Systems.Englewood Cliffs, N.J.: Prentice Hall, 1989.
[7] B.W. Johnson, Design and Analysis of Fault-Tolerant Digital Systems, pp. 394-402. Reading, Mass.: Addison-Wesley, June 1989.
[8] T.R.N. Rao, Error Coding for Arithmetic Processors.New York: Academic Press, 1974.
[9] F. Halsall, Data Communications, Computer Networks and Open Systems. Addison-Wesley, 1996.
[10] D.H. Lehmer, Proc. Second Symp. Large-Scale Digital Calculating Machinery, pp. 141-146, 1951.
[11] R. Zimmermann et al., A 177 Mb/s VLSI Implementation of the International Data Encryption Algorithm IEEE} J. Solid-State Circuits, vol. 29, no. 3, pp. 303-307, 1994.
[12] A. Curiger, VLSI Architectures for Computations in Finite Rings and Fields PhD thesis, Swiss Federal Inst. of Technology (ETH), Zurich, 1993.
[13] X. Lai and J. Massey,“A proposal for a new block encryption standard,” Advances in Cryptology: Proc. EUROCRYPT’90, pp. 389-404,Berlin, Springer-Verlag, 1991.
[14] Y. Ma, A Simplified Architecture for Modulo$(2^n+1)$Multiplication IEEE Trans. Computers, vol. 47, no. 3, pp. 333-337, Mar. 1998.
[15] L.M. Leibowitz, A Simplified Binary Arithmetic for the Fermat Number Transform IEEE Trans. Acoustics, Speech, Signal Processing, vol. 24, pp. 356-359, 1976.
[16] W.K. Jenkins, “The Design of Specialized Residue Classes for Efficient Recursive Digital Filter Realization,” IEEE Trans. Acoustics, Speech, and Signal Processing, vol. 30, pp. 370-380, 1982.
[17] W.K. Jenkins, “Recent Advance in Residue Number Techniques for Recursive Digital Filtering,” IEEE Trans. Acoustics, Speech, and Signal Processing, vol. 27, pp. 19-30, 1979.
[18] R.E. Ladner and M.J. Fischer, "Parallel Prefix Computation," J. ACM, vol. 27, no. 4, pp. 831-838, Oct. 1980.
[19] P.M. Kogge and H.S. Stone, A Parallel Algorithm for the Efficient Solution of a General Class of Recurrence Equations IEEE Trans. Computers, vol. 22, no. 8, pp. 783-791, Aug. 1973.
[20] S. Knowles, “A Family of Adders,” Proc. 15th IEEE Symp. Computer Arithmetic, pp. 277-281, Apr. 2001.
[21] J.A. Abraham and D.D. Gajski, Easily Testable High-Speed Realization of Register-Transfer-Level Operations Proc. 10th Fault-Tolerant Computing Symp. (FTCS-10), pp. 339-344, Oct. 1980.
[22] C. Efstathiou, D. Nikolos, and J. Kalamatianos, Area-Time Efficient Modulo$2^n-1$Adder Design IEEE Trans. Circuits and Systems II, vol. 41, no. 7, pp. 463-467, 1994.
[23] L. Kalampoukas et al., High-Speed Parallel-Prefix Modulo$2^n-1$Adders IEEE Trans. Computers, vol. 49, no. 7, pp. 673-680, July 2000.
[24] R. Zimmerman, Efficient VLSI Implementation of Modulo$(2^n\pm 1)$Addition and Multiplication Proc. 14th IEEE Symp. Computer Arithmetic, pp. 158-167, Apr. 1999.
[25] H.T. Vergos et al., Diminished-One Modulo$2^n+1$Adder Design IEEE Trans. Computers, vol. 51, pp. 1389-1399, 2002.
[26] A. Tyagi, A Reduced-Area Scheme for Carry-Select Adders IEEE Trans. Computers, vol. 42, no. 10, Oct. 1993.
[27] J.F. Wakerly, One's Complement Adder Eliminates Unwanted Zero Electronics, pp. 103-105, 5 Feb. 1976.
[28] J.J. Shedletsky, Comment on the Sequential and Indeterminate Behavior of an End-Around-Carry Adder IEEE Trans. Computers, vol. 26, no. 3, pp. 271-272, Mar. 1977.

Index Terms:
modulo 2n± 1 adders, select-prefix adders, computer arithmetic, VLSI architectures.
Citation:
Costas Efstathiou, Haridimos T. Vergos, Dimitris Nikolos, "Modulo 2n ± 1 Adder Design Using Select-Prefix Blocks," IEEE Transactions on Computers, vol. 52, no. 11, pp. 1399-1406, Nov. 2003, doi:10.1109/TC.2003.1244938
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