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On Combining Temporal Partitioning and Sharing of Functional Units in Compilation for Reconfigurable Architectures
October 2003 (vol. 52 no. 10)
pp. 1362-1375

Abstract—Resource virtualization on FPGA devices, achievable due to its dynamic reconfiguration capabilities, provides an attractive solution to save silicon area. Architectural synthesis for dynamically reconfigurable FPGA-based digital systems needs to consider the case of reducing the number of temporal partitions (reconfigurations) by enabling sharing of some functional units in the same temporal partition. This paper proposes a novel algorithm for automated datapath design from behavioral input descriptions (represented by an acyclic dataflow graph), which simultaneously performs temporal partitioning and sharing of functional units. The proposed algorithm attempts to minimize both the number of temporal partitions and the execution latency of the generated solution. Temporal partitioning, resource sharing, scheduling, and a simple form of allocation and binding are all integrated in a single task. The algorithm is based on heuristics and on a new concept of construction by gradually enlarging timing slots. Results show the efficiency and effectiveness of the algorithm when compared to existent approaches.

[1] N. Bhat, Novel Techniques for High Performance Field Programmable Logic Devices PhD thesis, Univ. of California, Berkeley, Electronic Research Laboratory, UCB/ERL-93-80, Nov. 1993.
[2] X.-P. Long and H. Amano, WASMII: A Data Driven Computer on a Virtual Hardware Proc. First IEEE Workshop Field Programmable Custom Computing Machines (FCCM '93), pp. 33-42, Apr. 1993.
[3] A. DeHon, Reconfigurable Architectures for General Purpose Computing PhD Thesis, AI Technical Report 1586, Massachusetts Inst. of Technology, Cambridge, Sept. 1996, http://www.ai.mit.edu/people/andrephd.html .
[4] Xilinx Inc., Virtex Field Programmable Gate Arrays, 1999.
[5] B. Schoner, C. Jones, and J. Villasenor, Issues in Wireless Coding Using Run-Time-Reconfigurable FPGAs Proc. IEEE Workshop FPGAs for Custom Computing Machines (FCCM '95), P. Athanas and K.L. Pocek, eds., pp. 85-89, Apr. 1996.
[6] R.D. Hudson, D.I. Lehn, and P.M. Athanas, A Run-Time Reconfigurable Engine for Image Interpolation Proc. Sixth IEEE Symp. Field-Programmable Custom Computing Machines (FCCM '98), K.L. Pocek and J. Arnold, eds., pp. 88-95, Apr. 1998.
[7] T. Fahringer and E. Mehofer, “Buffer-Safe and Cost-Driven Communication Optimization,” J. Parallel and Distributed Computing, vol. 57, pp. 33-63, 1999.
[8] D. Jones and D. Lewis, A Time-Multiplexed FPGA Architecture for Logic Emulation Proc. IEEE Custom Integrated Circuits Conference (CICC '95), pp. 495-498, May 1995.
[9] S. Trimberger, D. Carberry, A. Johnson, and J. Wong, “A Time-Multiplexed FPGA,” Proc. IEEE Workshop FPGAs for Custom Computing Machines, pp. 22-28, Apr. 1997.
[10] S.M. Scalera and J.R. Vázquez, The Design and Implementation of a Context Switching FPGA Proc. Sxth IEEE Symp. Field-Programmable Custom Computing Machines (FCCM '98), K.L. Pocek and J. Arnolds, eds., pp. 78-85, Apr. 1998.
[11] T. Fujii et al., A Dynamically Reconfigurable Logic Engine with a Multi-Context/Multi-Mode Unified-Cell Architecture Proc. IEEE Int'l Solid State Circuits Conf. (ISSCC '99), pp. 364-373, Feb. 1999, .
[12] S. Trimberger, Scheduling Designs into a Time-Multiplexed FPGA Proc. Sixth ACM Int'l Symp. Field Programmable Gate Arrays (FPGA '98), pp. 153-160, Feb. 1998.
[13] H. Liu and D.F. Wong, Circuit Partitioning for Dynamically Reconfigurable FPGAs Proc. Seventh ACM Int'l Symp. Field Programmable Gate Arrays (FPGA '99), pp. 187-194, Feb. 1999.
[14] D. Chang and M. Marek-Sadowska, Buffer Minimization and Time-Multiplexed I/O on Dynamically Reconfigurable FPGAs Proc. Fifth ACM/SIGDA Int'l Symp. Field Programmable Gate Arrays (FPGA '97), pp. 142-148, 1997.
[15] D. Gajski et al., High-Level Synthesis, Introduction to Chip and System Design. Kluwer Academic, 1992.
[16] I. Ouaiss et al., An Integrated Partitioning and Synthesis System for Dynamically Reconfigurable Multi-FPGA Architectures Proc. Fifth Reconfigurable Architectures Workshop (RAW '98), pp. 31-36, Mar. 1998.
[17] K.M. GajjalaPurna and D. Bhatia, Temporal Partitioning and Scheduling Data Flow Graphs for Reconfigurable Computers IEEE Trans. Computers, vol. 48, no. 6, pp. 579-591, June 1999.
[18] J.M.P. Cardoso and H.C. Neto, Compilation for FPGA-Based Reconfigurable Hardware IEEE Design and Test of Computers, vol. 20, no. 2, pp. 65-75, Mar./Apr. 2003.
[19] R. Jain, A. Parker, and N. Park, Module Selection for Pipelined Synthesis Proc. 25th IEEE/ACM Design Automation Conf. (DAC '88), pp. 542-547, June 1988.
[20] P.G. Paulin, J.P. Knight, and E.F. Girczyc, HAL: A Multi-Paradigm Approach to Automatic Data Path Synthesis Proc. 23rd IEEE/ACM Design Automation Conf. (DAC '86), pp. 263-270, 1986.
[21] P. Dewilde, E. Deprettere, and R. Nouta, Parallel and Pipelined VLSI Implementation of Signal Processing Algorithms VLSI and Modern Signal Processing, S.Y. Kung, H.J. Whitehouse, T. Kailath, eds., pp. 258-264, Prentice Hall, 1985.
[22] D.J. Mallon and P.B. Denyer, “A New Approach to Pipeline Optimisation,” Proc. European Design Automation Conf. (EDAC-90), pp. 83-88, 1990.
[23] Texas Instruments, Inc., Viterbi V.32 PSTN Trellis Decoder, http://www.isscc.org/digests/1999/DATA/21_3.pdfhttp:/ /www.ti.com/sc/docs/products/ dsp/c6000/benchmarks62x.htm#filters, 1997.
[24] K.E. Batcher, Sorting Networks and Their Applications Proc. AFIPs Spring Joint Computer Conf., vol. 32, pp. 307-314, 1968.
[25] M. Narasimhan and J. Ramanujam, A Fast Approach to Computing Exact Solutions to the Resource-Constrained Scheduling Problem ACM Trans. Design Automation of Electronic Systems (TODAES), vol. 6, no. 4, pp. 490-500, Oct. 2001.
[26] P.-Y. Hsiao, G.-M. Wu, and J.-Y. Su, MPT-Based Branch-and-Bound Strategy for Scheduling Problem in High-Level Synthesis IEE Proc. Computers and Digital Techniques, vol. 145, no. 6, pp. 425-432, Nov. 1998.
[27] M.K. Dhodhi, F.H. Hielscher, R.H. Storer, and F. Bhasker, Datapath Synthesis Using a Problem-Space Genetic Algorithm IEEE Trans. CAD of Integrated Circuits and Systems, vol. 14, no. 8, pp. 934-944, Aug. 1995.
[28] X.-Y. Chen, X.-P. Ling, and H. Amano, Software Environment for WASMII: A Data Driven Machine with a Virtual Hardware Proc. Int'l Workshop Field-Programmable Logic and Applications (FPL '94), pp. 208-219, Sept. 1994.
[29] M. Gokhale and A. Marks, Automatic Synthesis of Parallel Programs Targeted to Dynamically Reconfigurable Logic Array Proc. Fifth Int'l Workshop Field Programmable Logic and Applications (FPL '95), W. Moore and W. Luk, eds., pp. 399-408, 1995.
[30] M. Vasilko and D. Ait-Boudaoud, Scheduling for Dynamically Reconfigurable FPGAs Proc. IFIP Int'l Workshop Logic and Architecture Synthesis (WLAS '95), pp. 328-336, Dec. 1995.
[31] M. Vasilko and D. Ait-Boudaoud, Architectural Synthesis Techniques for Dynamically Reconfigurable Logic Proc. Sixth Int'l Workshop Field-Programmable Logic and Applications (FPL '96), R.R. Hartenstein and M. Glesner, eds., pp. 290-296, Sept. 1996.
[32] M. Kaul and R. Vemuri, Optimal Temporal Partitioning and Synthesis for Reconfigurable Architectures Proc. Design, Automation, and Test in Europe (DATE '98), pp. 389-396, Feb. 1998.
[33] M. Kaul and R. Vemuri, Temporal Partitioning Combined with Design Space Exploration for Latency Minimization of Run-Time Reconfigured Designs Proc. Design, Automation, and Test in Europe (DATE '99), pp. 202-209, Feb. 1999.
[34] M. Kaul, R. Vemuri, S. Givindarajan, and I.E. Ouaiss, An Automated Temporal Partitioning and Loop Fission Approach to FPGA Based Reconfigurable Synthesis of DSP Applications Proc. IEEE/ACM Design Automation Conf. (DAC '99), 1999.
[35] A. Takayama, Y. Shibata, K. Iwai, and H. Amano, Dataflow Partitioning and Scheduling Algorithms for WASMII, a Virtual Hardware Proc. 10th Int'l Conf. Field-Programmable Logic and Applications (FPL '00), R.W. Hartenstein and H. Grünbacher, eds., pp. 685-694, Aug. 2000.
[36] J. Cardoso and H. Neto, "Macro-Based Hardware Compilation of Java Bytecodes into a Dynamic Reconfigurable Computing System," Proc. 7th IEEE Symp. FPGAs for Custom Computing Machines (FCCM 99), IEEE CS Press, 1999, pp. 2-11.
[37] R. Hudson, D. Lehn, J. Hess, J. Atwell, D. Moye, K. Shiring, and P. Athanas, Spatio-Temporal Partitioning of Computational Structures onto Configurable Computing Machines SPIE Proc. Configurable Computing: Technology and Applications, J. Schewel, ed., vol. 3526, pp. 62-71, Oct. 1998.
[38] J.M.P. Cardoso and H.C. Neto, An Enhanced Static-List Scheduling Algorithm for Temporal Partitioning onto RPUs Proc. 10th IFIP Int'l Conf. Very Large Scale Integration (VLSI '99), L.M. Silveira, S. Devadas and R. Reis, eds., pp. 485-496, Dec. 1999.
[39] S. Ganesan and R. Vemuri, An Integrated Temporal Partitioning and Partial Reconfiguration Technique for Design Latency Improvement Proc. Design, Automation&Test in Europe (DATE '00), pp. 320-325, Mar. 2000.
[40] X. Zhang, K. Ng, and W. Luk, A Combined Approach to High-Level Synthesis for Dynamically Reconfigurable Systems Proc. 10th Int'l Conf. Field-Programmable Logic and Applications (FPL '00), R.W. Hartenstein and H. Grünbacher, eds., pp. 361-370, Aug. 2000.
[41] N. Ramasubramanian, R. Subramanian, and S. Pande, Automatic Compilation of Loops to Exploit Operator Parallelism on Configurable Arithmetic Logic Units IEEE Trans. Parallel and Distributed Systems, vol. 13, no. 1, pp. 45-66, Jan. 2002.
[42] A. Pandey and R. Vemuri, Combined Temporal Partitioning and Scheduling for Reconfigurable Architectures Proc. SPIE Photonics East Conf., J. Schewel et al., eds., pp. 93-103, Sept. 1999.
[43] S.C. Goldstein, H. Schmit, M. Budiu, S. Cadambi, M. Moe, and R.R. Taylor, “PipeRench: A Reconfigurable Architecture and Compiler,” Computer, vol. 33, no. 4, pp. 70–77, Apr. 2000.

Index Terms:
FPGAs, reconfigurable computing, scheduling, temporal partitioning.
Citation:
Jo?o M.P. Cardoso, "On Combining Temporal Partitioning and Sharing of Functional Units in Compilation for Reconfigurable Architectures," IEEE Transactions on Computers, vol. 52, no. 10, pp. 1362-1375, Oct. 2003, doi:10.1109/TC.2003.1234532
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