This Article 
   
 Share 
   
 Bibliographic References 
   
 Add to: 
 
Digg
Furl
Spurl
Blink
Simpy
Google
Del.icio.us
Y!MyWeb
 
 Search 
   
A Systematic Method for Modifying March Tests for Bit-Oriented Memories into Tests for Word-Oriented Memories
October 2003 (vol. 52 no. 10)
pp. 1320-1331

Abstract—Most memory test algorithms are optimized for a particular memory technology and a particular set of fault models, under the assumption that the memory is bit-oriented, i.e., read and write operations affect only a single bit in the memory. Traditionally, word-oriented memories have been tested by repeated application of a test for bit-oriented memories, whereby a different data background is used during each application. This results in time inefficiencies and limited fault coverage. A systematic way of converting tests for bit-oriented memories into tests for word-oriented memories is presented, distinguishing between interword and intraword faults. The conversion consists of concatenating to the test for interword faults, a test for intraword faults. This approach results in more efficient tests with complete coverage of the targeted faults. Word-oriented memory tests are very important, because most memories have an external data path which is wider than one bit.

[1] R. Dekker, A Realistic Fault Model and Test Algorithms for Static Random Access Memories IEEE Trans. Computers, vol. 39, no. 6, pp. 567-572, June 1990.
[2] A.J. van de Goor, Testing Semiconductor Memories, Theory and Practice. Gouda, The Netherlands: ComTex Publishing,http://ce.et.tudelft.nl~vdgoor/, 1998.
[3] R.P. Treuer and V.K. Agarwal, Fault Location Algorithms for Repairable Embedded RAMs Proc. IEEE Int'l Test Conf., pp. 825-834, 1993.
[4] I.B.S. Tlili and A.J. van de Goor, Tests for Word-Oriented Memories Technical Report No. 1-68340-44(1997)08, Dept. of Electrical Eng., Delft Univ. of Technology, Delft, The Netherlands, 1997.
[5] A.J. van de Goor and I.B.S. Tlili, March Tests for Word-Oriented Memories Proc. Design Automation and Test in Europe, pp. 501-508, 1998.
[6] A.J. van de Goor, I.B.S. Tlili, and S. Hamdioui, Converting March Tests for Bit-Oriented Memories into Tests for Word-Oriented Memories Records IEEE Int'l Workshop Memory Technology, Design and Testing, pp. 46-52, 1998.
[7] R.D. Adams, Extentions of Static Random Access Memory Fault Modeling and Examination of Patterns for Fault Detection master's thesis, Thayer School of Eng., May 1996.
[8] A.J. van de Goor, G.N. Gaydadjiev, V.N. Yarmolik, and V.G. Mikitjuk, March LR: A Test for Realistic Linked Faults Proc. 14th VLSI Test Symp., pp. 272-280, 1996.
[9] P. Mazumder and J.H. Patel, Parallel Testing for Pattern-Sensitive Faults in Semiconductor Random-Access Memories IEEE Trans. Computers, vol. 38, no. 3, pp. 394-407, Mar. 1989.
[10] M. Nicolaidis, V. Castro Alves, and H. Bederr, "Testing Complex Couplings in Multiport RAMs," IEEE Trans. VLSI Systems, vol. 3, no. 1, pp. 59-71, Mar. 1995.
[11] B. Prince, Semiconductor Memories. Chichester, U.K.: John Wiley&Sons, 1991.
[12] A.J. van de Goor, G.N. Gaydadjiev, V.N. Yarmolik, and V.G. Mikitjuk, March LA: A Test for Linked Memory Faults Proc. European Design and Test Conf., pp. 627-627, 1997.

Index Terms:
Bit-oriented memories, word-oriented memories, march tests, data backgrounds, fault models.
Citation:
Ad J. van de Goor, Issam B.S. Tlili, "A Systematic Method for Modifying March Tests for Bit-Oriented Memories into Tests for Word-Oriented Memories," IEEE Transactions on Computers, vol. 52, no. 10, pp. 1320-1331, Oct. 2003, doi:10.1109/TC.2003.1234529
Usage of this product signifies your acceptance of the Terms of Use.