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Parallel CRC Realization
October 2003 (vol. 52 no. 10)
pp. 1312-1319

Abstract—This paper presents a theoretical result in the context of realizing high-speed hardware for parallel CRC checksums. Starting from the serial implementation widely reported in the literature, we have identified a recursive formula from which our parallel implementation is derived. In comparison with previous works, the new scheme is faster and more compact and is independent of the technology used in its realization. In our solution, the number of bits processed in parallel can be different from the degree of the polynomial generator. Last, we have also developed high-level parametric codes that are capable of generating the circuits autonomously when only the polyonomial is given.

[1] W.W. Peterson and D.T. Brown, Cyclic Codes for Error Detection Proc. IRE, Jan. 1961.
[2] A.S. Tanenbaum, Computer Networks. Prentice Hall, 1981.
[3] W. Stallings, Data and Computer Communications. Prentice Hall, 2000.
[4] T.V. Ramabadran and S.S. Gaitonde, A Tutorial on CRC Computations IEEE Micro, Aug. 1988.
[5] N.R. Saxena and E.J. McCluskey, Analysis of Checksums, Extended Precision Checksums and Cyclic Redundancy Checks IEEE Trans. Computers, July 1990.
[6] M.J.S. Smith, Application-Specific Integrated Circuits. Addison-Wesley Longman, Jan. 1998.
[7] G. Albertengo and R. Sisto, Parallel CRC Generation IEEE Micro, Oct. 1990.
[8] R. Lee, Cyclic Codes Redundancy Digital Design, July 1977.
[9] A. Perez, Byte-Wise CRC Calculations IEEE Micro, June 1983.
[10] A.K. Pandeya and T.J. Cassa, Parallel CRC Lets Many Lines Use One Circuit Computer Design, Sept. 1975.
[11] M. Braun et al., Parallel CRC Computation in FPGAs Proc. Workshop Field Programmable Logic and Applications, 1996.
[12] J. McCluskey, High Speed Calculation of Cyclic Redundancy Codes Proc. 1999 ACM/SIGDA Seventh Int'l Symp. Field Programmable Gate Arrays, p. 250, 1999.
[13] M. Spachmann, Automatic Generation of Parallel CRC Circuits IEEE Design and Test of Computers, May 2001.
[14] M.D. Shieh et al., A Systematic Approach for Parallel CRC Computations J. Information Science and Eng., May 2001.
[15] G. Griffiths and G. Carlyle Stones, The Tea-Leaf Reader Algorithm: An Efficient Implementation of CRC-16 and CRC-32 Comm. ACM, July 1987.
[16] D.V. Sarwate, Computation of Cyclic Redundancy Checks via Table Look-Up Comm. ACM, Aug. 1988.
[17] G.F. Franklin et al., Feedback Control of Dynamic Systems. Addison Wesley, 1994.
[18] J. Borges and J. Rifá, A Characterization of 1-Perfect Additive Codes Pirdi-1/98, 1998.

Index Terms:
Parallel CRC, LFSR, error-detection, VLSI, FPGA, VHDL, digital logic.
Citation:
Giuseppe Campobello, Giuseppe Patan?, Marco Russo, "Parallel CRC Realization," IEEE Transactions on Computers, vol. 52, no. 10, pp. 1312-1319, Oct. 2003, doi:10.1109/TC.2003.1234528
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