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IC Bridge Fault Modeling for IP Blocks Using Neural Network-Based VHDL Saboteurs
October 2003 (vol. 52 no. 10)
pp. 1285-1297

Abstract—This paper presents a new bridge fault model, suitable for IP blocks, that is based on a multiple layer feedforward neural network and implemented within the framework of a VHDL saboteur cell. Empirical evidence and experimental results show that it satisfies a prescribed set of bridge fault model criteria better than any existing approach. The new model computes bridged node voltages and propagation delay times with due attention to surrounding circuit elements. This is especially significant since, with the exception of full analog defect simulation, no other technique even attempts to model the delay effects of bridge defects. Yet, compared to these analog simulations, the new approach is several orders of magnitude faster and, for a 0.35u cell library, is able to compute bridged node voltages with an average error near 0.006 volts and propagation delay times with an average error near 14 ps. Furthermore, dealing with a concept that has not previously been considered in related research, the new model is validated with respect to deep-submicron technologies for limited gate-count circuit modules.

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Index Terms:
Bridge defects, fault models, neural networks, VHDL, CMOS ICs, fault simulation, IP blocks.
Citation:
Donald B. Shaw, Dhamin Al-Khalili, C?me N. Rozon, "IC Bridge Fault Modeling for IP Blocks Using Neural Network-Based VHDL Saboteurs," IEEE Transactions on Computers, vol. 52, no. 10, pp. 1285-1297, Oct. 2003, doi:10.1109/TC.2003.1234526
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