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Donald B. Shaw, Dhamin AlKhalili, C?me N. Rozon, "IC Bridge Fault Modeling for IP Blocks Using Neural NetworkBased VHDL Saboteurs," IEEE Transactions on Computers, vol. 52, no. 10, pp. 12851297, October, 2003.  
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@article{ 10.1109/TC.2003.1234526, author = {Donald B. Shaw and Dhamin AlKhalili and C?me N. Rozon}, title = {IC Bridge Fault Modeling for IP Blocks Using Neural NetworkBased VHDL Saboteurs}, journal ={IEEE Transactions on Computers}, volume = {52}, number = {10}, issn = {00189340}, year = {2003}, pages = {12851297}, doi = {http://doi.ieeecomputersociety.org/10.1109/TC.2003.1234526}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }  
RefWorks Procite/RefMan/Endnote  x  
TY  JOUR JO  IEEE Transactions on Computers TI  IC Bridge Fault Modeling for IP Blocks Using Neural NetworkBased VHDL Saboteurs IS  10 SN  00189340 SP1285 EP1297 EPD  12851297 A1  Donald B. Shaw, A1  Dhamin AlKhalili, A1  C?me N. Rozon, PY  2003 KW  Bridge defects KW  fault models KW  neural networks KW  VHDL KW  CMOS ICs KW  fault simulation KW  IP blocks. VL  52 JA  IEEE Transactions on Computers ER   
Abstract—This paper presents a new bridge fault model, suitable for IP blocks, that is based on a multiple layer feedforward neural network and implemented within the framework of a VHDL saboteur cell. Empirical evidence and experimental results show that it satisfies a prescribed set of bridge fault model criteria better than any existing approach. The new model computes bridged node voltages and propagation delay times with due attention to surrounding circuit elements. This is especially significant since, with the exception of full analog defect simulation, no other technique even attempts to model the delay effects of bridge defects. Yet, compared to these analog simulations, the new approach is several orders of magnitude faster and, for a 0.35u cell library, is able to compute bridged node voltages with an average error near 0.006 volts and propagation delay times with an average error near 14 ps. Furthermore, dealing with a concept that has not previously been considered in related research, the new model is validated with respect to deepsubmicron technologies for limited gatecount circuit modules.
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