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Adaptive Algorithms for Maximal Diagnosis of Wiring Interconnects
October 2003 (vol. 52 no. 10)
pp. 1259-1270

Abstract—We give two algorithms for maximal diagnosis of wiring networks without repair under a general fault model. Maximal diagnosis consists of identifying all diagnosable faults under the assumptions that each net can have multiple drivers and receivers and can be affected by any number of short and open faults. This process is equivalent to verifying all connections between inputs and outputs. Matrices represent the connections in fault-free and faulty networks. We present two new algorithms and discuss prior algorithms. All algorithms discussed are adaptive and have their tests divided into two phases. Our first new algorithm exploits a unique condition for verifying the connections; our second new algorithm maps the connection verification problem to a bipartite graph. All algorithms discussed use an independent test set for the first test phase. Simulation results show that the proposed algorithms outperform previous algorithms for maximal diagnosis in terms of the number of tests. The total time complexity for computing the test sequences and analyzing the output response is polynomial.

[1] J.C. Chan, Boundary Walking Test: An Accelerated Scan Method for Greater System Reliability IEEE Trans. Reliability, vol. 41, no. 4, pp. 496-503, 1992.
[2] W.-T. Cheng, J.L. Lewandowski, and E. Wu, "Diagnosis for Wiring Interconnects," Proc. Int'l Test Conf., pp. 565-571, 1990.
[3] C. Feng, W.K. Huang, and F. Lombardi, "A New Diagnosis Approach for Short Faults in Interconnects," Proc. IEEE Int'l Symp. Fault-Tolerant Computing (FTCS-25), IEEE CS Press, 1995, pp. 331-338.
[4] M. Garey, D. Johnson, and H. So, An Application of Graph Coloring to Printed Circuit Testing IEEE Trans. Circuits and Systems, vol. 23, no. 10, pp. 591-599, 1976.
[5] P. Goel and M.T. McMahon, Electronic Chip In-Place Test Proc. IEEE Int'l Test Conf., pp. 83-90, 1982.
[6] A. Hassan, J. Rajski, and V.K. Agrawal, Testing and Diagnosis of Interconnects Using Boundary-Scan Proc. IEEE Int'l Test Conf., pp. 126-137, 1985.
[7] N. Jarwala and C.W. Yau, "A New Framework for Analyzing Test Generation and Diagnosis Algorithms for Wiring Interconnects," Proc. Int'l Test Conf., pp. 63-70, 1989.
[8] W.H. Kautz, Testing for Faults in Wiring Networks IEEE Trans. Computers, vol. 23, no. 4, pp. 358-363, Apr. 1974.
[9] V. Krishnamurthy, Combinatorics Theory and Applications. Ellis Horwood, 1986.
[10] J.C. Lien and M.A. Breuer, "Maximal Diagnosis for Wiring Networks," Proc. IEEE Int'l Test Conf. (ITC 91), IEEE CS Press, Los Alamitos, Calif., 1991, pp. 96-105.
[11] T. Liu, X.-T. Chen, F. Lombardi, and J. Salinas, Layout-Driven Detection of Bridge Faults in Interconnects Proc. IEEE Symp. DFT in VLSI Systems, pp. 105-113, 1996.
[12] T. Liu, F. Lombardi, and J. Salinas, “Diagnosis of Interconnects and FPICs Using a Structured Walking-1 Approach,” Proc. IEEE VLSI Test Symp., pp. 256-261, 1995.
[13] D. McBean and W.R. Moore, "Testing Interconnects: A Pin Adjacency Approach," Proc. European Test Conf., pp. 484-490, 1993.
[14] S. Park, A New Complete Diagnosis Patterns for Wiring Interconnects Proc. IEEE/ACM Design Automation Conf., pp. 203-208, June 1996.
[15] J. Salinas, Y.-N. Shen, and F. Lombardi, A Sweeping Line Approach to Interconnect Testing IEEE Trans. Computers, vol. 45, no. 8, pp. 917-929, Aug. 1996.
[16] W. Shi and K. Fuchs, "Optimal Interconnect Diagnosis of Wiring Networks," IEEE Trans. Very Large Scale Integration (VLSI) Systems, vol. 3, no. 2, June 1995, pp. 430-436.
[17] P.T. Wagner, Interconnect Testing with Boundary Scan Proc. IEEE Int'l Test Conf., pp. 52-57, 1987.
[18] C.W. Yau and N. Jarwala, "A Unified Theory for Designing Optimal Test Generation and Diagnosis Algorithms for Board Interconnects," Proc. Int'l Test Conf., pp. 71-77, 1989.

Index Terms:
Wiring network, interconnect, adaptive diagnosis, multiple faults.
Wen-Yi Feng, Fred J. Meyer, Fabrizio Lombardi, "Adaptive Algorithms for Maximal Diagnosis of Wiring Interconnects," IEEE Transactions on Computers, vol. 52, no. 10, pp. 1259-1270, Oct. 2003, doi:10.1109/TC.2003.1234524
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